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git01.mediatek.com / filogic / uboot / c9285bf61ab39091553fce5c8871797a55f31f07 / . / configs / evb-rk3288_defconfig
blob: c2b1f0f69635324b1236f08e5197ff0d3d2877ee [file] [log] [blame]
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x00000000
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]4CONFIG_SYS_MALLOC_F_LEN=0x2000
5CONFIG_ROCKCHIP_RK3288=y
Philipp Tomsich798370f2017-06-29 11:21:15 +0200[diff] [blame]6CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]7CONFIG_TARGET_EVB_RK3288=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame^]8CONFIG_NR_DRAM_BANKS=1
9CONFIG_SPL_STACK_R_ADDR=0x80000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]10CONFIG_DEBUG_UART_BASE=0xff690000
11CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]12CONFIG_DEBUG_UART=y
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]13# CONFIG_ANDROID_BOOT_IMAGE is not set
Simon Glass4458d3b2016-10-17 20:12:35 -0600[diff] [blame]14CONFIG_SILENT_CONSOLE=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]15CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]16# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]17CONFIG_DISPLAY_BOARDINFO_LATE=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]18CONFIG_SPL_STACK_R=y
19CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]20CONFIG_CMD_GPIO=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]21CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]22CONFIG_CMD_I2C=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]23CONFIG_CMD_MMC=y
24CONFIG_CMD_SF=y
25CONFIG_CMD_SPI=y
Eddie Caib3501fe2017-12-15 08:17:13 +0800[diff] [blame]26CONFIG_CMD_USB=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]27# CONFIG_CMD_SETEXPR is not set
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]28CONFIG_CMD_CACHE=y
29CONFIG_CMD_TIME=y
30CONFIG_CMD_PMIC=y
31CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]32# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]33# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]34CONFIG_SPL_PARTITION_UUIDS=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]35CONFIG_SPL_OF_CONTROL=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]36CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]37CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]38CONFIG_ENV_IS_IN_MMC=y
David Wu255f68e2018-01-13 13:53:55 +0800[diff] [blame]39CONFIG_NET_RANDOM_ETHADDR=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]40CONFIG_REGMAP=y
41CONFIG_SPL_REGMAP=y
42CONFIG_SYSCON=y
43CONFIG_SPL_SYSCON=y
44CONFIG_CLK=y
45CONFIG_SPL_CLK=y
Alex Kiernane80d2942018-05-29 15:30:55 +0000[diff] [blame]46CONFIG_FASTBOOT_FLASH=y
47CONFIG_FASTBOOT_FLASH_MMC_DEV=0
48CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]49CONFIG_ROCKCHIP_GPIO=y
50CONFIG_SYS_I2C_ROCKCHIP=y
51CONFIG_LED=y
52CONFIG_LED_GPIO=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]53CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]54CONFIG_MMC_DW_ROCKCHIP=y
Vignesh Re57ea112019-02-05 11:29:10 +0530[diff] [blame]55CONFIG_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]56CONFIG_SF_DEFAULT_SPEED=20000000
Jacob Chen5c3166d2017-02-23 14:20:17 +0800[diff] [blame]57CONFIG_DM_ETH=y
Jacob Chen5c3166d2017-02-23 14:20:17 +0800[diff] [blame]58CONFIG_ETH_DESIGNWARE=y
59CONFIG_GMAC_ROCKCHIP=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]60CONFIG_PINCTRL=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]61CONFIG_SPL_PINCTRL=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]62CONFIG_DM_PMIC=y
63CONFIG_PMIC_ACT8846=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]64CONFIG_REGULATOR_ACT8846=y
65CONFIG_DM_REGULATOR_FIXED=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]66CONFIG_PWM_ROCKCHIP=y
67CONFIG_RAM=y
68CONFIG_SPL_RAM=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]69CONFIG_DEBUG_UART_SHIFT=2
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]70CONFIG_SYSRESET=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]71CONFIG_USB=y
Tom Rini6c3798f2018-02-10 20:27:45 -0500[diff] [blame]72CONFIG_USB_DWC2=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]73CONFIG_ROCKCHIP_USB2_PHY=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]74CONFIG_USB_GADGET=y
Maxime Ripard7f78b9d2017-09-07 08:58:08 +0200[diff] [blame]75CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
76CONFIG_USB_GADGET_VENDOR_NUM=0x2207
77CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]78CONFIG_USB_GADGET_DWC2_OTG=y
Lukasz Majewskie364e4b2018-01-29 19:25:54 +0100[diff] [blame]79CONFIG_USB_FUNCTION_MASS_STORAGE=y
eric.gao@rock-chips.com9f127162017-06-21 11:22:03 +0800[diff] [blame]80CONFIG_DM_VIDEO=y
81CONFIG_DISPLAY=y
82CONFIG_VIDEO_ROCKCHIP=y
83CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
84CONFIG_DISPLAY_ROCKCHIP_MIPI=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]85CONFIG_USE_TINY_PRINTF=y
86CONFIG_CMD_DHRYSTONE=y
87CONFIG_ERRNO_STR=y