blob: 8bc3b1673ac47756ea3fde05769db3a13576dfe6 [file] [log] [blame]
developer3f661952020-11-12 16:35:56 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8/dts-v1/;
9
10#include <dt-bindings/gpio/gpio.h>
11#include "mt7620.dtsi"
12
13/ {
14 compatible = "mediatek,mt7620-mt7530-rfb", "mediatek,mt7620-soc";
15 model = "MediaTek MT7620-MT7530 RFB (MTKC712)";
16
17 aliases {
18 serial0 = &uartlite;
19 spi0 = &spi0;
20 };
21
22 chosen {
23 stdout-path = &uartlite;
24 };
25};
26
27&uartlite {
28 status = "okay";
29};
30
31&pinctrl {
32 state_default: pin_state {
33 pleds {
34 groups = "ephy led", "wled";
35 function = "led";
36 };
37
38 gpios {
39 groups = "pa", "uartf";
40 function = "gpio";
41 };
42 };
43
44 gsw_pins: gsw_pins {
45 mdio {
46 groups = "mdio";
47 function = "mdio";
48 };
49
50 rgmii1 {
51 groups = "rgmii1";
52 function = "rgmii1";
53 };
54 };
55};
56
57&spi0 {
58 status = "okay";
59 num-cs = <2>;
60
61 spi-flash@0 {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "jedec,spi-nor";
65 spi-max-frequency = <25000000>;
66 reg = <0>;
67 };
68};
69
70&gpio0 {
71 pa0_pull_low {
72 gpio-hog;
73 output-low;
74 gpios = <20 GPIO_ACTIVE_HIGH>;
75 };
76
77 pa1_pull_low {
78 gpio-hog;
79 output-low;
80 gpios = <21 GPIO_ACTIVE_HIGH>;
81 };
82};
83
84&eth {
85 status = "okay";
86
87 pinctrl-names = "default";
88 pinctrl-0 = <&gsw_pins>;
89
90 port5 {
91 phy-mode = "rgmii";
92 phy-addr = <5>;
93 fixed-link {
94 full-duplex;
95 speed = <1000>;
96 mediatek,mt7530;
97 mediatek,mt7530-reset = <&gpio0 10 GPIO_ACTIVE_HIGH>;
98 };
99 };
100};