| Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
| 9 | #include <asm/pl310.h> |
| 10 | #include <asm/u-boot.h> |
| 11 | #include <asm/utils.h> |
| 12 | #include <image.h> |
| 13 | #include <asm/arch/reset_manager.h> |
| 14 | #include <spl.h> |
| 15 | #include <asm/arch/system_manager.h> |
| 16 | #include <asm/arch/freeze_controller.h> |
| 17 | #include <asm/arch/clock_manager.h> |
| 18 | #include <asm/arch/scan_manager.h> |
| 19 | #include <asm/arch/sdram.h> |
| 20 | #include <asm/arch/scu.h> |
| 21 | #include <asm/arch/nic301.h> |
| 22 | #include <asm/sections.h> |
| 23 | #include <fdtdec.h> |
| 24 | #include <watchdog.h> |
| 25 | #include <asm/arch/pinmux.h> |
| 26 | |
| 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
| 29 | static const struct socfpga_system_manager *sysmgr_regs = |
| 30 | (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
| 31 | |
| 32 | u32 spl_boot_device(void) |
| 33 | { |
| 34 | const u32 bsel = readl(&sysmgr_regs->bootinfo); |
| 35 | |
| 36 | switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { |
| 37 | case 0x1: /* FPGA (HPS2FPGA Bridge) */ |
| 38 | return BOOT_DEVICE_RAM; |
| 39 | case 0x2: /* NAND Flash (1.8V) */ |
| 40 | case 0x3: /* NAND Flash (3.0V) */ |
| 41 | socfpga_per_reset(SOCFPGA_RESET(NAND), 0); |
| 42 | return BOOT_DEVICE_NAND; |
| 43 | case 0x4: /* SD/MMC External Transceiver (1.8V) */ |
| 44 | case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ |
| 45 | socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); |
| 46 | socfpga_per_reset(SOCFPGA_RESET(DMA), 0); |
| 47 | return BOOT_DEVICE_MMC1; |
| 48 | case 0x6: /* QSPI Flash (1.8V) */ |
| 49 | case 0x7: /* QSPI Flash (3.0V) */ |
| 50 | socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); |
| 51 | return BOOT_DEVICE_SPI; |
| 52 | default: |
| 53 | printf("Invalid boot device (bsel=%08x)!\n", bsel); |
| 54 | hang(); |
| 55 | } |
| 56 | } |
| 57 | |
| 58 | #ifdef CONFIG_SPL_MMC_SUPPORT |
| 59 | u32 spl_boot_mode(const u32 boot_device) |
| 60 | { |
| 61 | #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) |
| 62 | return MMCSD_MODE_FS; |
| 63 | #else |
| 64 | return MMCSD_MODE_RAW; |
| 65 | #endif |
| 66 | } |
| 67 | #endif |
| 68 | |
| 69 | void spl_board_init(void) |
| 70 | { |
| 71 | /* configuring the clock based on handoff */ |
| 72 | cm_basic_init(gd->fdt_blob); |
| 73 | WATCHDOG_RESET(); |
| 74 | |
| 75 | config_dedicated_pins(gd->fdt_blob); |
| 76 | WATCHDOG_RESET(); |
| 77 | |
| 78 | /* Release UART from reset */ |
| 79 | socfpga_reset_uart(0); |
| 80 | |
| 81 | /* enable console uart printing */ |
| 82 | preloader_console_init(); |
| 83 | } |
| 84 | |
| 85 | void board_init_f(ulong dummy) |
| 86 | { |
| 87 | /* |
| 88 | * Configure Clock Manager to use intosc clock instead external osc to |
| 89 | * ensure success watchdog operation. We do it as early as possible. |
| 90 | */ |
| 91 | cm_use_intosc(); |
| 92 | |
| 93 | socfpga_watchdog_disable(); |
| 94 | |
| 95 | arch_early_init_r(); |
| 96 | |
| 97 | #ifdef CONFIG_HW_WATCHDOG |
| 98 | /* release osc1 watchdog timer 0 from reset */ |
| 99 | socfpga_reset_deassert_osc1wd0(); |
| 100 | |
| 101 | /* reconfigure and enable the watchdog */ |
| 102 | hw_watchdog_init(); |
| 103 | WATCHDOG_RESET(); |
| 104 | #endif /* CONFIG_HW_WATCHDOG */ |
| 105 | } |