Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2016 Google, Inc |
maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _ASM_ARCH_WDT_H |
| 7 | #define _ASM_ARCH_WDT_H |
| 8 | |
| 9 | #define WDT_BASE 0x1e785000 |
| 10 | |
| 11 | /* |
| 12 | * Special value that needs to be written to counter_restart register to |
| 13 | * (re)start the timer |
| 14 | */ |
| 15 | #define WDT_COUNTER_RESTART_VAL 0x4755 |
| 16 | |
| 17 | /* Control register */ |
| 18 | #define WDT_CTRL_RESET_MODE_SHIFT 5 |
| 19 | #define WDT_CTRL_RESET_MODE_MASK 3 |
| 20 | |
| 21 | #define WDT_CTRL_EN (1 << 0) |
| 22 | #define WDT_CTRL_RESET (1 << 1) |
| 23 | #define WDT_CTRL_CLK1MHZ (1 << 4) |
| 24 | #define WDT_CTRL_2ND_BOOT (1 << 7) |
| 25 | |
| 26 | /* Values for Reset Mode */ |
| 27 | #define WDT_CTRL_RESET_SOC 0 |
| 28 | #define WDT_CTRL_RESET_CHIP 1 |
| 29 | #define WDT_CTRL_RESET_CPU 2 |
| 30 | #define WDT_CTRL_RESET_MASK 3 |
| 31 | |
| 32 | /* Reset Mask register */ |
| 33 | #define WDT_RESET_ARM (1 << 0) |
| 34 | #define WDT_RESET_COPROC (1 << 1) |
| 35 | #define WDT_RESET_SDRAM (1 << 2) |
| 36 | #define WDT_RESET_AHB (1 << 3) |
| 37 | #define WDT_RESET_I2C (1 << 4) |
| 38 | #define WDT_RESET_MAC1 (1 << 5) |
| 39 | #define WDT_RESET_MAC2 (1 << 6) |
| 40 | #define WDT_RESET_GCRT (1 << 7) |
| 41 | #define WDT_RESET_USB20 (1 << 8) |
| 42 | #define WDT_RESET_USB11_HOST (1 << 9) |
| 43 | #define WDT_RESET_USB11_EHCI2 (1 << 10) |
| 44 | #define WDT_RESET_VIDEO (1 << 11) |
| 45 | #define WDT_RESET_HAC (1 << 12) |
| 46 | #define WDT_RESET_LPC (1 << 13) |
| 47 | #define WDT_RESET_SDSDIO (1 << 14) |
| 48 | #define WDT_RESET_MIC (1 << 15) |
| 49 | #define WDT_RESET_CRT2C (1 << 16) |
| 50 | #define WDT_RESET_PWM (1 << 17) |
| 51 | #define WDT_RESET_PECI (1 << 18) |
| 52 | #define WDT_RESET_JTAG (1 << 19) |
| 53 | #define WDT_RESET_ADC (1 << 20) |
| 54 | #define WDT_RESET_GPIO (1 << 21) |
| 55 | #define WDT_RESET_MCTP (1 << 22) |
| 56 | #define WDT_RESET_XDMA (1 << 23) |
| 57 | #define WDT_RESET_SPI (1 << 24) |
| 58 | #define WDT_RESET_MISC (1 << 25) |
| 59 | |
| 60 | #ifndef __ASSEMBLY__ |
| 61 | struct ast_wdt { |
| 62 | u32 counter_status; |
| 63 | u32 counter_reload_val; |
| 64 | u32 counter_restart; |
| 65 | u32 ctrl; |
| 66 | u32 timeout_status; |
| 67 | u32 clr_timeout_status; |
| 68 | u32 reset_width; |
maxims@google.com | df35df2 | 2017-04-17 12:00:22 -0700 | [diff] [blame] | 69 | /* On pre-ast2500 SoCs this register is reserved. */ |
maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 70 | u32 reset_mask; |
maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 71 | }; |
| 72 | |
maxims@google.com | df35df2 | 2017-04-17 12:00:22 -0700 | [diff] [blame] | 73 | /** |
| 74 | * Given flags parameter passed to wdt_reset or wdt_start uclass functions, |
| 75 | * gets Reset Mode value from it. |
| 76 | * |
| 77 | * @flags: flags parameter passed into wdt_reset or wdt_start |
| 78 | * @return Reset Mode value |
| 79 | */ |
| 80 | u32 ast_reset_mode_from_flags(ulong flags); |
| 81 | |
| 82 | /** |
| 83 | * Given flags parameter passed to wdt_reset or wdt_start uclass functions, |
| 84 | * gets Reset Mask value from it. Reset Mask is only supported on ast2500 |
| 85 | * |
| 86 | * @flags: flags parameter passed into wdt_reset or wdt_start |
| 87 | * @return Reset Mask value |
| 88 | */ |
| 89 | u32 ast_reset_mask_from_flags(ulong flags); |
| 90 | |
| 91 | /** |
| 92 | * Given Reset Mask and Reset Mode values, converts them to flags, |
| 93 | * suitable for passing into wdt_start or wdt_reset uclass functions. |
| 94 | * |
| 95 | * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they |
| 96 | * can both be packed into single 32 bits wide value. |
| 97 | * |
| 98 | * @reset_mode: Reset Mode |
| 99 | * @reset_mask: Reset Mask |
| 100 | */ |
| 101 | ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask); |
maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 102 | #endif /* __ASSEMBLY__ */ |
| 103 | |
| 104 | #endif /* _ASM_ARCH_WDT_H */ |