blob: 6825c07df35f42c9023008c22e1e9d429ad44dd6 [file] [log] [blame]
Dave Gerlach278e7ac2021-04-23 11:27:46 -05001// SPDX-License-Identifier: GPL-2.0
2/*
Roger Quadrosaf6e2a72023-08-05 11:14:40 +03003 * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
Dave Gerlach278e7ac2021-04-23 11:27:46 -05004 */
5
Roger Quadrosaf6e2a72023-08-05 11:14:40 +03006#include "k3-am642-evm.dts"
Dave Gerlach3daecde2021-05-04 18:00:52 -05007#include "k3-am64-evm-ddr4-1600MTs.dtsi"
8#include "k3-am64-ddr.dtsi"
Dave Gerlach278e7ac2021-04-23 11:27:46 -05009
Roger Quadrosaf6e2a72023-08-05 11:14:40 +030010#include "k3-am642-evm-u-boot.dtsi"
Dave Gerlach278e7ac2021-04-23 11:27:46 -050011
Roger Quadrosaf6e2a72023-08-05 11:14:40 +030012/ {
Dave Gerlach278e7ac2021-04-23 11:27:46 -050013 aliases {
14 remoteproc0 = &sysctrler;
15 remoteproc1 = &a53_0;
16 };
17
Dave Gerlach278e7ac2021-04-23 11:27:46 -050018 a53_0: a53@0 {
19 compatible = "ti,am654-rproc";
20 reg = <0x00 0x00a90000 0x00 0x10>;
21 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
Manorit Chawdhry99aceb82023-04-14 09:47:57 +053022 <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
23 <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
Dave Gerlach278e7ac2021-04-23 11:27:46 -050024 resets = <&k3_reset 135 0>;
25 clocks = <&k3_clks 61 0>;
26 assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
27 assigned-clock-parents = <&k3_clks 61 2>;
28 assigned-clock-rates = <200000000>, <1000000000>;
29 ti,sci = <&dmsc>;
30 ti,sci-proc-id = <32>;
31 ti,sci-host-id = <10>;
Simon Glassd3a98cb2023-02-13 08:56:33 -070032 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -050033 };
34
Dave Gerlach278e7ac2021-04-23 11:27:46 -050035 clk_200mhz: dummy-clock-200mhz {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <200000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -070039 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -050040 };
41};
42
Roger Quadros3405e9c2023-09-29 16:46:41 +030043&vtt_supply {
44 bootph-pre-ram;
45};
46
Dave Gerlach278e7ac2021-04-23 11:27:46 -050047&cbass_main {
48 sysctrler: sysctrler {
49 compatible = "ti,am654-system-controller";
50 mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
51 mbox-names = "tx", "rx";
Simon Glassd3a98cb2023-02-13 08:56:33 -070052 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -050053 };
54};
55
Roger Quadrosaf6e2a72023-08-05 11:14:40 +030056&main_esm {
Simon Glassd3a98cb2023-02-13 08:56:33 -070057 bootph-pre-ram;
Hari Nagalla789225e2022-03-09 14:42:29 -060058};
59
Roger Quadros3405e9c2023-09-29 16:46:41 +030060&cbass_mcu {
61 bootph-pre-ram;
62};
63
Roger Quadrosaf6e2a72023-08-05 11:14:40 +030064&mcu_esm {
Simon Glassd3a98cb2023-02-13 08:56:33 -070065 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -050066};
67
68&dmsc {
69 mboxes= <&secure_proxy_main 0>,
70 <&secure_proxy_main 1>,
71 <&secure_proxy_main 0>;
72 mbox-names = "rx", "tx", "notify";
73 ti,host-id = <35>;
74 ti,secure-host;
75};
76
Roger Quadros12fdc4c2023-09-29 16:46:42 +030077&vtt_supply {
78 bootph-pre-ram;
79};
80
81&memorycontroller {
82 vtt-supply = <&vtt_supply>;
83};
84
Dave Gerlach278e7ac2021-04-23 11:27:46 -050085&sdhci0 {
Dave Gerlach278e7ac2021-04-23 11:27:46 -050086 clocks = <&clk_200mhz>;
87 clock-names = "clk_xin";
Dave Gerlach278e7ac2021-04-23 11:27:46 -050088};
89
90&sdhci1 {
Dave Gerlach278e7ac2021-04-23 11:27:46 -050091 clocks = <&clk_200mhz>;
92 clock-names = "clk_xin";
Dave Gerlach278e7ac2021-04-23 11:27:46 -050093};
94
Nishanth Menond6a453c2021-05-04 18:00:55 -050095&main_gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070096 bootph-pre-ram;
Nishanth Menond6a453c2021-05-04 18:00:55 -050097};
98
Roger Quadrosaf6e2a72023-08-05 11:14:40 +030099/* UART is initialized before SYSFW is started
100 * so we can't do any power-domain/clock operations.
101 * Delete clock/power-domain properties to avoid
102 * UART init failure
103 */
104&main_uart0 {
Lokesh Vutlae1c5a5d2021-05-06 16:44:57 +0530105 /delete-property/ power-domains;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300106 /delete-property/ clocks;
107 /delete-property/ clock-names;
Aswath Govindraju0b2481e2021-06-04 22:00:36 +0530108};
109
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300110/* timer init is called as part of rproc_start() while
111 * starting System Firmware, so any clock/power-domain
112 * operations will fail as SYSFW is not yet up and running.
113 * Delete all clock/power-domain properties to avoid
114 * timer init failure.
115 * This is an always on timer at 20MHz.
116 */
117&main_timer0 {
118 /delete-property/ clocks;
119 /delete-property/ assigned-clocks;
120 /delete-property/ assigned-clock-parents;
121 /delete-property/ power-domains;
Aswath Govindraju0b2481e2021-06-04 22:00:36 +0530122};
Jonathan Humphreyse1ce4f42024-02-23 18:17:02 -0600123
124&ospi0 {
125 reg = <0x00 0x0fc40000 0x00 0x100>,
126 <0x00 0x60000000 0x00 0x8000000>;
127};