Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
Roger Quadros | af6e2a7 | 2023-08-05 11:14:40 +0300 | [diff] [blame] | 3 | * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
Roger Quadros | af6e2a7 | 2023-08-05 11:14:40 +0300 | [diff] [blame] | 6 | #include "k3-am642-evm.dts" |
Dave Gerlach | 3daecde | 2021-05-04 18:00:52 -0500 | [diff] [blame] | 7 | #include "k3-am64-evm-ddr4-1600MTs.dtsi" |
| 8 | #include "k3-am64-ddr.dtsi" |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 9 | |
Roger Quadros | af6e2a7 | 2023-08-05 11:14:40 +0300 | [diff] [blame] | 10 | #include "k3-am642-evm-u-boot.dtsi" |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 11 | |
Roger Quadros | af6e2a7 | 2023-08-05 11:14:40 +0300 | [diff] [blame] | 12 | / { |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 13 | aliases { |
| 14 | remoteproc0 = &sysctrler; |
| 15 | remoteproc1 = &a53_0; |
| 16 | }; |
| 17 | |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 18 | a53_0: a53@0 { |
| 19 | compatible = "ti,am654-rproc"; |
| 20 | reg = <0x00 0x00a90000 0x00 0x10>; |
| 21 | power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, |
Manorit Chawdhry | 99aceb8 | 2023-04-14 09:47:57 +0530 | [diff] [blame] | 22 | <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, |
| 23 | <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 24 | resets = <&k3_reset 135 0>; |
| 25 | clocks = <&k3_clks 61 0>; |
| 26 | assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; |
| 27 | assigned-clock-parents = <&k3_clks 61 2>; |
| 28 | assigned-clock-rates = <200000000>, <1000000000>; |
| 29 | ti,sci = <&dmsc>; |
| 30 | ti,sci-proc-id = <32>; |
| 31 | ti,sci-host-id = <10>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 32 | bootph-pre-ram; |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 33 | }; |
| 34 | |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 35 | clk_200mhz: dummy-clock-200mhz { |
| 36 | compatible = "fixed-clock"; |
| 37 | #clock-cells = <0>; |
| 38 | clock-frequency = <200000000>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 39 | bootph-pre-ram; |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 40 | }; |
| 41 | }; |
| 42 | |
Roger Quadros | 3405e9c | 2023-09-29 16:46:41 +0300 | [diff] [blame] | 43 | &vtt_supply { |
| 44 | bootph-pre-ram; |
| 45 | }; |
| 46 | |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 47 | &cbass_main { |
| 48 | sysctrler: sysctrler { |
| 49 | compatible = "ti,am654-system-controller"; |
| 50 | mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; |
| 51 | mbox-names = "tx", "rx"; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 52 | bootph-pre-ram; |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 53 | }; |
| 54 | }; |
| 55 | |
Roger Quadros | af6e2a7 | 2023-08-05 11:14:40 +0300 | [diff] [blame] | 56 | &main_esm { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 57 | bootph-pre-ram; |
Hari Nagalla | 789225e | 2022-03-09 14:42:29 -0600 | [diff] [blame] | 58 | }; |
| 59 | |
Roger Quadros | 3405e9c | 2023-09-29 16:46:41 +0300 | [diff] [blame] | 60 | &cbass_mcu { |
| 61 | bootph-pre-ram; |
| 62 | }; |
| 63 | |
Roger Quadros | af6e2a7 | 2023-08-05 11:14:40 +0300 | [diff] [blame] | 64 | &mcu_esm { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 65 | bootph-pre-ram; |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 66 | }; |
| 67 | |
| 68 | &dmsc { |
| 69 | mboxes= <&secure_proxy_main 0>, |
| 70 | <&secure_proxy_main 1>, |
| 71 | <&secure_proxy_main 0>; |
| 72 | mbox-names = "rx", "tx", "notify"; |
| 73 | ti,host-id = <35>; |
| 74 | ti,secure-host; |
| 75 | }; |
| 76 | |
Roger Quadros | 12fdc4c | 2023-09-29 16:46:42 +0300 | [diff] [blame] | 77 | &vtt_supply { |
| 78 | bootph-pre-ram; |
| 79 | }; |
| 80 | |
| 81 | &memorycontroller { |
| 82 | vtt-supply = <&vtt_supply>; |
| 83 | }; |
| 84 | |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 85 | &sdhci0 { |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 86 | clocks = <&clk_200mhz>; |
| 87 | clock-names = "clk_xin"; |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | &sdhci1 { |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 91 | clocks = <&clk_200mhz>; |
| 92 | clock-names = "clk_xin"; |
Dave Gerlach | 278e7ac | 2021-04-23 11:27:46 -0500 | [diff] [blame] | 93 | }; |
| 94 | |
Nishanth Menon | d6a453c | 2021-05-04 18:00:55 -0500 | [diff] [blame] | 95 | &main_gpio0 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 96 | bootph-pre-ram; |
Nishanth Menon | d6a453c | 2021-05-04 18:00:55 -0500 | [diff] [blame] | 97 | }; |
| 98 | |
Roger Quadros | af6e2a7 | 2023-08-05 11:14:40 +0300 | [diff] [blame] | 99 | /* UART is initialized before SYSFW is started |
| 100 | * so we can't do any power-domain/clock operations. |
| 101 | * Delete clock/power-domain properties to avoid |
| 102 | * UART init failure |
| 103 | */ |
| 104 | &main_uart0 { |
Lokesh Vutla | e1c5a5d | 2021-05-06 16:44:57 +0530 | [diff] [blame] | 105 | /delete-property/ power-domains; |
Roger Quadros | af6e2a7 | 2023-08-05 11:14:40 +0300 | [diff] [blame] | 106 | /delete-property/ clocks; |
| 107 | /delete-property/ clock-names; |
Aswath Govindraju | 0b2481e | 2021-06-04 22:00:36 +0530 | [diff] [blame] | 108 | }; |
| 109 | |
Roger Quadros | af6e2a7 | 2023-08-05 11:14:40 +0300 | [diff] [blame] | 110 | /* timer init is called as part of rproc_start() while |
| 111 | * starting System Firmware, so any clock/power-domain |
| 112 | * operations will fail as SYSFW is not yet up and running. |
| 113 | * Delete all clock/power-domain properties to avoid |
| 114 | * timer init failure. |
| 115 | * This is an always on timer at 20MHz. |
| 116 | */ |
| 117 | &main_timer0 { |
| 118 | /delete-property/ clocks; |
| 119 | /delete-property/ assigned-clocks; |
| 120 | /delete-property/ assigned-clock-parents; |
| 121 | /delete-property/ power-domains; |
Aswath Govindraju | 0b2481e | 2021-06-04 22:00:36 +0530 | [diff] [blame] | 122 | }; |
Jonathan Humphreys | e1ce4f4 | 2024-02-23 18:17:02 -0600 | [diff] [blame] | 123 | |
| 124 | &ospi0 { |
| 125 | reg = <0x00 0x0fc40000 0x00 0x100>, |
| 126 | <0x00 0x60000000 0x00 0x8000000>; |
| 127 | }; |