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git01.mediatek.com / filogic / uboot / cb3ed624b0616a75038c9e25f662b851ac6b4599 / . / arch / arm / dts / dra7-ipu-common-early-boot.dtsi
blob: afa4595195b919096f1300c06df93a85d7326972 [file] [log] [blame]
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame]3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]4 */
5
6/ {
7 chosen {
8 firmware-loader = &fs_loader0;
9 };
10
11 fs_loader0: fs_loader@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-all;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]13 compatible = "u-boot,fs-loader";
14 phandlepart = <&mmc1 1>;
15 };
16
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
20 ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]22
23 ipu2_memory_region: ipu2-memory@95800000 {
24 compatible = "shared-dma-pool";
25 reg = <0x0 0x95800000 0x0 0x3800000>;
26 reusable;
27 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]29 };
30
31 ipu1_memory_region: ipu1-memory@9d000000 {
32 compatible = "shared-dma-pool";
33 reg = <0x0 0x9d000000 0x0 0x2000000>;
34 reusable;
35 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]37 };
38
39 ipu1_pgtbl: ipu1-pgtbl@95700000 {
40 reg = <0x0 0x95700000 0x0 0x40000>;
41 no-map;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]43 };
44
45 ipu2_pgtbl: ipu2-pgtbl@95740000 {
46 reg = <0x0 0x95740000 0x0 0x40000>;
47 no-map;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]49 };
50 };
51};
52
53&timer3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]55};
56
57&timer4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]59};
60
61&timer7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]63};
64
65&timer8 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]67};
68
69&timer9 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]71};
72
73&timer11 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]75};
76
77&mmu_ipu1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]79};
80
81&mmu_ipu2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]83};
84
85&ipu1 {
86 status = "okay";
87 memory-region = <&ipu1_memory_region>;
88 pg-tbl = <&ipu1_pgtbl>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]90};
91
92&ipu2 {
93 status = "okay";
94 memory-region = <&ipu2_memory_region>;
95 pg-tbl = <&ipu2_pgtbl>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]97};
98
99&l4_wkup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]101};
102
103&prm {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]105};
106
107&ipu1_rst {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]109};
110
111&ipu2_rst {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Keerthy1efd5e22022-01-27 13:16:57 +0100[diff] [blame]113};