| Govindraj.R | edc16a0 | 2012-02-06 03:55:34 +0000 | [diff] [blame] | 1 | /* |
| 2 | * OMAP EHCI port support |
| 3 | * Based on LINUX KERNEL |
| 4 | * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c |
| 5 | * |
| 6 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com* |
| 7 | * Author: Govindraj R <govindraj.raja@ti.com> |
| 8 | * |
| 9 | * This program is free software: you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 of |
| 11 | * the License as published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 20 | */ |
| 21 | |
| 22 | #ifndef _OMAP_COMMON_EHCI_H_ |
| 23 | #define _OMAP_COMMON_EHCI_H_ |
| 24 | |
| 25 | enum usbhs_omap_port_mode { |
| 26 | OMAP_USBHS_PORT_MODE_UNUSED, |
| 27 | OMAP_EHCI_PORT_MODE_PHY, |
| 28 | OMAP_EHCI_PORT_MODE_TLL, |
| 29 | OMAP_EHCI_PORT_MODE_HSIC, |
| 30 | }; |
| 31 | |
| 32 | #ifdef CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS |
| 33 | #define OMAP_HS_USB_PORTS CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS |
| 34 | #else |
| 35 | #define OMAP_HS_USB_PORTS 3 |
| 36 | #endif |
| 37 | |
| 38 | #define is_ehci_phy_mode(x) ((x) == OMAP_EHCI_PORT_MODE_PHY) |
| 39 | #define is_ehci_tll_mode(x) ((x) == OMAP_EHCI_PORT_MODE_TLL) |
| 40 | #define is_ehci_hsic_mode(x) ((x) == OMAP_EHCI_PORT_MODE_HSIC) |
| 41 | |
| 42 | /* Values of UHH_REVISION - Note: these are not given in the TRM */ |
| 43 | #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */ |
| 44 | #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */ |
| 45 | |
| 46 | /* UHH Register Set */ |
| 47 | #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) |
| 48 | #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) |
| 49 | #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) |
| 50 | #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) |
| 51 | |
| 52 | #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS 1 |
| 53 | #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) |
| 54 | #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) |
| 55 | #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31) |
| 56 | |
| 57 | #define OMAP_P1_MODE_CLEAR (3 << 16) |
| 58 | #define OMAP_P1_MODE_TLL (1 << 16) |
| 59 | #define OMAP_P1_MODE_HSIC (3 << 16) |
| 60 | #define OMAP_P2_MODE_CLEAR (3 << 18) |
| 61 | #define OMAP_P2_MODE_TLL (1 << 18) |
| 62 | #define OMAP_P2_MODE_HSIC (3 << 18) |
| 63 | #define OMAP_P3_MODE_HSIC (3 << 20) |
| 64 | |
| 65 | /* EHCI Register Set */ |
| 66 | #define EHCI_INSNREG04_DISABLE_UNSUSPEND (1 << 5) |
| 67 | #define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31 |
| 68 | #define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24 |
| 69 | #define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22 |
| 70 | #define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16 |
| 71 | |
| 72 | #define OMAP_REV1_TLL_CHANNEL_COUNT 3 |
| 73 | #define OMAP_REV2_TLL_CHANNEL_COUNT 2 |
| 74 | |
| 75 | /* TLL Register Set */ |
| 76 | #define OMAP_TLL_CHANNEL_CONF(num) (0x004 * num) |
| 77 | #define OMAP_TLL_CHANNEL_CONF_DRVVBUS (1 << 16) |
| 78 | #define OMAP_TLL_CHANNEL_CONF_CHRGVBUS (1 << 15) |
| 79 | #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) |
| 80 | #define OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI (2 << 1) |
| 81 | #define OMAP_TLL_CHANNEL_CONF_CHANEN 1 |
| 82 | |
| 83 | struct omap_usbhs_board_data { |
| 84 | enum usbhs_omap_port_mode port_mode[OMAP_HS_USB_PORTS]; |
| 85 | }; |
| 86 | |
| 87 | struct omap_usbtll { |
| 88 | u32 rev; /* 0x00 */ |
| 89 | u32 hwinfo; /* 0x04 */ |
| 90 | u8 reserved1[0x8]; |
| 91 | u32 sysc; /* 0x10 */ |
| 92 | u32 syss; /* 0x14 */ |
| 93 | u32 irqst; /* 0x18 */ |
| 94 | u32 irqen; /* 0x1c */ |
| 95 | u8 reserved2[0x10]; |
| 96 | u32 shared_conf; /* 0x30 */ |
| 97 | u8 reserved3[0xc]; |
| 98 | u32 channel_conf; /* 0x40 */ |
| 99 | }; |
| 100 | |
| 101 | struct omap_uhh { |
| 102 | u32 rev; /* 0x00 */ |
| 103 | u32 hwinfo; /* 0x04 */ |
| 104 | u8 reserved1[0x8]; |
| 105 | u32 sysc; /* 0x10 */ |
| 106 | u32 syss; /* 0x14 */ |
| 107 | u8 reserved2[0x28]; |
| 108 | u32 hostconfig; /* 0x40 */ |
| 109 | u32 debugcsr; /* 0x44 */ |
| 110 | }; |
| 111 | |
| 112 | struct omap_ehci { |
| 113 | u32 hccapbase; /* 0x00 */ |
| 114 | u32 hcsparams; /* 0x04 */ |
| 115 | u32 hccparams; /* 0x08 */ |
| 116 | u8 reserved1[0x04]; |
| 117 | u32 usbcmd; /* 0x10 */ |
| 118 | u32 usbsts; /* 0x14 */ |
| 119 | u32 usbintr; /* 0x18 */ |
| 120 | u32 frindex; /* 0x1c */ |
| 121 | u32 ctrldssegment; /* 0x20 */ |
| 122 | u32 periodiclistbase; /* 0x24 */ |
| 123 | u32 asysnclistaddr; /* 0x28 */ |
| 124 | u8 reserved2[0x24]; |
| 125 | u32 configflag; /* 0x50 */ |
| 126 | u32 portsc_i; /* 0x54 */ |
| 127 | u8 reserved3[0x38]; |
| 128 | u32 insreg00; /* 0x90 */ |
| 129 | u32 insreg01; /* 0x94 */ |
| 130 | u32 insreg02; /* 0x98 */ |
| 131 | u32 insreg03; /* 0x9c */ |
| 132 | u32 insreg04; /* 0xa0 */ |
| 133 | u32 insreg05_utmi_ulpi; /* 0xa4 */ |
| 134 | u32 insreg06; /* 0xa8 */ |
| 135 | u32 insreg07; /* 0xac */ |
| 136 | u32 insreg08; /* 0xb0 */ |
| 137 | }; |
| 138 | |
| 139 | int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata); |
| 140 | int omap_ehci_hcd_stop(void); |
| 141 | |
| 142 | #endif /* _OMAP_COMMON_EHCI_H_ */ |