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git01.mediatek.com / filogic / uboot / f6975e2d48d048e248c9a9434a861c5fe2fc7201 / . / arch / arm / dts / imx8mp-dhcom-u-boot.dtsi
blob: a29db0ddd3f1cc67fc43c91942561b095077e81d [file] [log] [blame]
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mp-u-boot.dtsi"
7
8/ {
9 aliases {
10 eeprom0 = &eeprom0;
11 eeprom1 = &eeprom1;
12 mmc0 = &usdhc2; /* MicroSD */
13 mmc1 = &usdhc3; /* eMMC */
14 mmc2 = &usdhc1; /* SDIO */
15 };
16
17 config {
18 dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>;
19 };
20
21 wdt-reboot {
22 compatible = "wdt-reboot";
23 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]25 };
26};
27
28&buck4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]30};
31
32&buck5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]34};
35
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]36&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]38};
39
40&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]42};
43
44&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]46};
47
48&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]50};
51
52&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]54};
55
56&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]58};
59
60&pinctrl_i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]62};
63
64&pinctrl_i2c3_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]66};
67
68&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]70};
71
72&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]74};
75
76&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]78};
79
80&pinctrl_usdhc2_100mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]82};
83
84&pinctrl_usdhc2_200mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]86};
87
88&pinctrl_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]90};
91
92&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]94};
95
96&pinctrl_usdhc3_100mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]98};
99
100&pinctrl_usdhc3_100mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]102};
103
104&pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]105 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]106
107 regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]109 };
110};
111
112&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]114};
115
116&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]118};
119
120/* SDIO WiFi */
121&usdhc1 {
122 status = "disabled";
123};
124
125&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]127};
128
129&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]130 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]131};
132
133&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]134 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]135};
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]136
137&binman {
138 itb {
139 fit {
140 images {
141 fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast {
142 description = "imx8mp-dhcom-som-overlay-eth1xfast";
143 type = "flat_dt";
144 compression = "none";
145
146 blob-ext {
147 filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo";
148 };
149 };
150
151 fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast {
152 description = "imx8mp-dhcom-som-overlay-eth2xfast";
153 type = "flat_dt";
154 compression = "none";
155
156 blob-ext {
157 filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo";
158 };
159 };
160
161 fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast {
162 description = "imx8mp-dhcom-pdk-overlay-eth2xfast";
163 type = "flat_dt";
164 compression = "none";
165
166 blob-ext {
167 filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo";
168 };
169 };
Marek Vasut792cb562023-09-21 20:44:18 +0200[diff] [blame]170
171 fdt-dto-imx8mp-dhcom-som-overlay-rev100 {
172 description = "imx8mp-dhcom-som-overlay-rev100";
173 type = "flat_dt";
174 compression = "none";
175
176 blob-ext {
177 filename = "imx8mp-dhcom-som-overlay-rev100.dtbo";
178 };
179 };
180
Marek Vasuteaee3032023-09-21 20:44:20 +0200[diff] [blame]181 fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 {
182 description = "imx8mp-dhcom-pdk3-overlay-rev100";
Marek Vasut792cb562023-09-21 20:44:18 +0200[diff] [blame]183 type = "flat_dt";
184 compression = "none";
185
186 blob-ext {
Marek Vasuteaee3032023-09-21 20:44:20 +0200[diff] [blame]187 filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo";
Marek Vasut792cb562023-09-21 20:44:18 +0200[diff] [blame]188 };
189 };
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]190 };
191
192 configurations {
193 default = "@config-DEFAULT-SEQ";
194
195 @config-SEQ {
196 fdt = "fdt-1",
197 "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast",
198 "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast",
Marek Vasut792cb562023-09-21 20:44:18 +0200[diff] [blame]199 "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast",
200 "fdt-dto-imx8mp-dhcom-som-overlay-rev100",
Marek Vasuteaee3032023-09-21 20:44:20 +0200[diff] [blame]201 "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100";
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]202 };
203 };
204 };
205 };
206};