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git01.mediatek.com / filogic / uboot / 60ffb9cafd0879b98e3ad4d96fd961ee963a485c / . / arch / arm / dts / rk3308-u-boot.dtsi
blob: 26e1a94f2e1a9c57121a0139aeff78456dff28ad [file] [log] [blame]
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 *(C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
Quentin Schulzd9ffa5e2022-09-02 15:10:52 +0200[diff] [blame]6#include "rockchip-u-boot.dtsi"
7
Kever Yangd4d2b222020-01-08 17:38:48 +0800[diff] [blame]8/ {
9 aliases {
10 mmc0 = &emmc;
11 mmc1 = &sdmmc;
12 };
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000[diff] [blame]13
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]14 chosen {
15 u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
16 };
17
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000[diff] [blame]18 otp: nvmem@ff210000 {
19 compatible = "rockchip,rk3308-otp";
20 reg = <0x0 0xff210000 0x0 0x4000>;
21 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
22 <&cru PCLK_OTP_PHY>;
23 clock-names = "otp", "apb_pclk", "phy";
24 resets = <&cru SRST_OTP_PHY>;
25 reset-names = "phy";
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 cpu_id: id@7 {
30 reg = <0x07 0x10>;
31 };
32 };
Jonas Karlmanfbced692024-04-08 18:14:02 +0000[diff] [blame]33
34 rng: rng@ff2f0000 {
35 compatible = "rockchip,cryptov2-rng";
36 reg = <0x0 0xff2f0000 0x0 0x4000>;
37 };
Kever Yangd4d2b222020-01-08 17:38:48 +0800[diff] [blame]38};
39
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]40&cru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-all;
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]42};
43
44&dmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-all;
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]46};
47
48&emmc {
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]49 bootph-pre-ram;
50 bootph-some-ram;
51
Andy Yan134eb022019-11-26 21:15:38 +0800[diff] [blame]52 /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
53 u-boot,spl-fifo-mode;
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]54};
55
56&emmc_bus8 {
57 bootph-pre-ram;
58 bootph-some-ram;
59};
60
61&emmc_clk {
62 bootph-pre-ram;
63 bootph-some-ram;
64};
65
66&emmc_cmd {
67 bootph-pre-ram;
68 bootph-some-ram;
69};
70
71&grf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-all;
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]73};
74
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]75&pcfg_pull_none {
Pegorer Massimof8cc29b2023-07-15 10:19:40 +0000[diff] [blame]76 bootph-all;
Pegorer Massimof8cc29b2023-07-15 10:19:40 +0000[diff] [blame]77};
78
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]79&pcfg_pull_none_4ma {
80 bootph-pre-ram;
81 bootph-some-ram;
82};
83
84&pcfg_pull_none_8ma {
85 bootph-pre-ram;
86 bootph-some-ram;
87};
88
89&pcfg_pull_up {
90 bootph-all;
91};
92
93&pcfg_pull_up_4ma {
94 bootph-pre-ram;
95 bootph-some-ram;
96};
97
98&pcfg_pull_up_8ma {
99 bootph-pre-ram;
100 bootph-some-ram;
101};
102
103&pinctrl {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-all;
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]105};
106
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]107&rtc_32k {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-all;
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]109};
110
111&sdmmc {
112 bootph-pre-ram;
113 bootph-some-ram;
114
115 /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
116 u-boot,spl-fifo-mode;
117};
118
119&sdmmc_bus4 {
120 bootph-pre-ram;
121 bootph-some-ram;
122};
123
124&sdmmc_clk {
125 bootph-pre-ram;
126 bootph-some-ram;
127};
128
129&sdmmc_cmd {
130 bootph-pre-ram;
131 bootph-some-ram;
132};
133
134&sdmmc_det {
135 bootph-pre-ram;
136 bootph-some-ram;
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]137};