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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wenyou Yang8c772bd2016-07-20 17:55:12 +08002/*
3 * Copyright (C) 2016 Atmel Corporation
4 * Wenyou.Yang <wenyou.yang@atmel.com>
Wenyou Yang8c772bd2016-07-20 17:55:12 +08005 */
6
7#include <common.h>
8#include <clk-uclass.h>
Simon Glass11c89f32017-05-17 17:18:03 -06009#include <dm.h>
Wenyou Yang6b66b922017-09-05 18:30:07 +080010#include <syscon.h>
Wenyou Yang8c772bd2016-07-20 17:55:12 +080011#include <linux/io.h>
12#include <mach/at91_pmc.h>
Wenyou Yang6b66b922017-09-05 18:30:07 +080013#include <mach/sama5_sfr.h>
Wenyou Yang8c772bd2016-07-20 17:55:12 +080014#include "pmc.h"
15
Wenyou Yang6b66b922017-09-05 18:30:07 +080016/*
17 * The purpose of this clock is to generate a 480 MHz signal. A different
18 * rate can't be configured.
19 */
20#define UTMI_RATE 480000000
Wenyou Yang8c772bd2016-07-20 17:55:12 +080021
22static int utmi_clk_enable(struct clk *clk)
23{
24 struct pmc_platdata *plat = dev_get_platdata(clk->dev);
25 struct at91_pmc *pmc = plat->reg_base;
Wenyou Yang6b66b922017-09-05 18:30:07 +080026 struct clk clk_dev;
27 ulong clk_rate;
28 u32 utmi_ref_clk_freq;
Wenyou Yang8c772bd2016-07-20 17:55:12 +080029 u32 tmp;
Wenyou Yang6b66b922017-09-05 18:30:07 +080030 int err;
Wenyou Yang8c772bd2016-07-20 17:55:12 +080031
32 if (readl(&pmc->sr) & AT91_PMC_LOCKU)
33 return 0;
34
Wenyou Yang6b66b922017-09-05 18:30:07 +080035 /*
36 * If mainck rate is different from 12 MHz, we have to configure the
37 * FREQ field of the SFR_UTMICKTRIM register to generate properly
38 * the utmi clock.
39 */
40 err = clk_get_by_index(clk->dev, 0, &clk_dev);
41 if (err)
42 return -EINVAL;
43
44 clk_rate = clk_get_rate(&clk_dev);
45 switch (clk_rate) {
46 case 12000000:
47 utmi_ref_clk_freq = 0;
48 break;
49 case 16000000:
50 utmi_ref_clk_freq = 1;
51 break;
52 case 24000000:
53 utmi_ref_clk_freq = 2;
54 break;
55 /*
56 * Not supported on SAMA5D2 but it's not an issue since MAINCK
57 * maximum value is 24 MHz.
58 */
59 case 48000000:
60 utmi_ref_clk_freq = 3;
61 break;
62 default:
63 printf("UTMICK: unsupported mainck rate\n");
64 return -EINVAL;
65 }
66
67 if (plat->regmap_sfr) {
68 err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
69 if (err)
70 return -EINVAL;
71
72 tmp &= ~AT91_UTMICKTRIM_FREQ;
73 tmp |= utmi_ref_clk_freq;
74 err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
75 if (err)
76 return -EINVAL;
77 } else if (utmi_ref_clk_freq) {
78 printf("UTMICK: sfr node required\n");
79 return -EINVAL;
80 }
81
Wenyou Yang8c772bd2016-07-20 17:55:12 +080082 tmp = readl(&pmc->uckr);
83 tmp |= AT91_PMC_UPLLEN |
84 AT91_PMC_UPLLCOUNT |
85 AT91_PMC_BIASEN;
86 writel(tmp, &pmc->uckr);
87
88 while (!(readl(&pmc->sr) & AT91_PMC_LOCKU))
89 ;
90
91 return 0;
92}
93
94static ulong utmi_clk_get_rate(struct clk *clk)
95{
Wenyou Yang6b66b922017-09-05 18:30:07 +080096 /* UTMI clk rate is fixed. */
97 return UTMI_RATE;
Wenyou Yang8c772bd2016-07-20 17:55:12 +080098}
99
100static struct clk_ops utmi_clk_ops = {
101 .enable = utmi_clk_enable,
102 .get_rate = utmi_clk_get_rate,
103};
104
Wenyou Yang6b66b922017-09-05 18:30:07 +0800105static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
106{
107 struct pmc_platdata *plat = dev_get_platdata(dev);
108 struct udevice *syscon;
109
110 uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
111 "regmap-sfr", &syscon);
112
113 if (syscon)
114 plat->regmap_sfr = syscon_get_regmap(syscon);
115
116 return 0;
117}
118
Wenyou Yang8c772bd2016-07-20 17:55:12 +0800119static int utmi_clk_probe(struct udevice *dev)
120{
121 return at91_pmc_core_probe(dev);
122}
123
124static const struct udevice_id utmi_clk_match[] = {
125 { .compatible = "atmel,at91sam9x5-clk-utmi" },
126 {}
127};
128
129U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
130 .name = "at91sam9x5-utmi-clk",
131 .id = UCLASS_CLK,
132 .of_match = utmi_clk_match,
133 .probe = utmi_clk_probe,
Wenyou Yang6b66b922017-09-05 18:30:07 +0800134 .ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
Wenyou Yang8c772bd2016-07-20 17:55:12 +0800135 .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
136 .ops = &utmi_clk_ops,
137};