blob: 8a145a5f742b0447e159c661dab08775e3281942 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese93e6bf42014-10-22 12:13:17 +02002/*
Stefan Roesec03a2132016-01-07 14:03:11 +01003 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
Stefan Roese93e6bf42014-10-22 12:13:17 +02004 */
5
Tom Rinidec7ea02024-05-20 13:35:03 -06006#include <config.h>
Stefan Roesebb1c0bd2015-06-29 14:58:13 +02007#include <ahci.h>
Simon Glass1d91ba72019-11-14 12:57:37 -07008#include <cpu_func.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060010#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060011#include <linux/delay.h>
Stefan Roesebb1c0bd2015-06-29 14:58:13 +020012#include <linux/mbus.h>
Stefan Roese93e6bf42014-10-22 12:13:17 +020013#include <asm/io.h>
Stefan Roese8aee4d32015-05-18 16:09:43 +000014#include <asm/pl310.h>
Stefan Roese93e6bf42014-10-22 12:13:17 +020015#include <asm/arch/cpu.h>
16#include <asm/arch/soc.h>
Marek Behúnee76b4a2021-08-16 15:19:37 +020017#include <asm/spl.h>
Stefan Roesed3e34732015-06-29 14:58:10 +020018#include <sdhci.h>
Stefan Roese93e6bf42014-10-22 12:13:17 +020019
20#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
21#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
22
Pali Rohár32301ee2022-09-09 14:41:28 +020023static const struct mbus_win windows[] = {
Stefan Roese93e6bf42014-10-22 12:13:17 +020024 /* SPI */
Stefan Roese13b109f2015-07-01 12:55:07 +020025 { MBUS_SPI_BASE, MBUS_SPI_SIZE,
26 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
Stefan Roese93e6bf42014-10-22 12:13:17 +020027
Pali Rohárdca22e52023-02-03 21:34:27 +010028 /* BootROM */
Stefan Roese13b109f2015-07-01 12:55:07 +020029 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
30 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
Chris Packhama8f845e2019-04-11 22:22:50 +120031
32#ifdef CONFIG_ARMADA_MSYS
33 /* DFX */
34 { MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
35#endif
Stefan Roese93e6bf42014-10-22 12:13:17 +020036};
37
Pali Rohár465ecee2023-02-03 21:41:45 +010038/* SPI0 CS0 Flash of size MBUS_SPI_SIZE is mapped to address MBUS_SPI_BASE */
Tony Dinhf362eaa2024-06-05 17:12:01 -070039#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && CONFIG_ENV_SPI_BUS == 0 && CONFIG_ENV_SPI_CS == 0 && \
Pali Rohár465ecee2023-02-03 21:41:45 +010040 CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE <= MBUS_SPI_SIZE
41void *env_sf_get_env_addr(void)
42{
43 return (void *)MBUS_SPI_BASE + CONFIG_ENV_OFFSET;
44}
45#endif
46
Stefan Roesee1b7bfd2015-08-25 14:09:12 +020047void lowlevel_init(void)
48{
49 /*
50 * Dummy implementation, we only need LOWLEVEL_INIT
51 * on Armada to configure CP15 in start.S / cpu_init_cp15()
52 */
53}
54
Marek Behún514628c2024-04-04 09:51:00 +020055#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)
Harald Seiler6f14d5f2020-12-15 16:47:52 +010056void reset_cpu(void)
Stefan Roese93e6bf42014-10-22 12:13:17 +020057{
58 struct mvebu_system_registers *reg =
59 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
60
61 writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
62 writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
63 while (1)
64 ;
65}
Marek Behún514628c2024-04-04 09:51:00 +020066#endif
Stefan Roese93e6bf42014-10-22 12:13:17 +020067
Marek Behúnee76b4a2021-08-16 15:19:37 +020068u32 get_boot_device(void)
69{
70 u32 val;
71 u32 boot_device;
Pali Rohár7e1aa722023-03-27 23:11:50 +020072 u32 boot_err_mode;
73#ifdef CONFIG_ARMADA_38X
74 u32 boot_err_code;
75#endif
Marek Behúnee76b4a2021-08-16 15:19:37 +020076
77 /*
Tom Rinib056ce402021-09-01 07:52:08 -040078 * First check, if UART boot-mode is active. This can only
79 * be done, via the bootrom error register. Here the
80 * MSB marks if the UART mode is active.
81 */
Tom Rini3327dd72022-03-30 18:07:12 -040082 val = readl(BOOTROM_ERR_REG);
Pali Rohár7e1aa722023-03-27 23:11:50 +020083 boot_err_mode = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
84 debug("BOOTROM_ERR_REG=0x%08x boot_err_mode=0x%x\n", val, boot_err_mode);
85 if (boot_err_mode == BOOTROM_ERR_MODE_UART)
Marek Behúnee76b4a2021-08-16 15:19:37 +020086 return BOOT_DEVICE_UART;
87
88#ifdef CONFIG_ARMADA_38X
89 /*
Tom Rinib056ce402021-09-01 07:52:08 -040090 * If the bootrom error code contains any other than zeros it's an
91 * error condition and the bootROM has fallen back to UART boot
92 */
Pali Rohár7e1aa722023-03-27 23:11:50 +020093 boot_err_code = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
94 debug("boot_err_code=0x%x\n", boot_err_code);
95 if (boot_err_code)
Marek Behúnee76b4a2021-08-16 15:19:37 +020096 return BOOT_DEVICE_UART;
97#endif
98
99 /*
Tom Rinib056ce402021-09-01 07:52:08 -0400100 * Now check the SAR register for the strapped boot-device
101 */
Tom Rini253b6a22022-12-04 10:13:42 -0500102 val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */
Marek Behúnee76b4a2021-08-16 15:19:37 +0200103 boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
104 debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
Marek Behúnee76b4a2021-08-16 15:19:37 +0200105#ifdef BOOT_FROM_NAND
Pali Roháre0c6d252023-03-29 21:03:32 +0200106 if (BOOT_FROM_NAND(boot_device))
Marek Behúnee76b4a2021-08-16 15:19:37 +0200107 return BOOT_DEVICE_NAND;
108#endif
109#ifdef BOOT_FROM_MMC
Pali Roháre0c6d252023-03-29 21:03:32 +0200110 if (BOOT_FROM_MMC(boot_device))
Marek Behúnee76b4a2021-08-16 15:19:37 +0200111 return BOOT_DEVICE_MMC1;
112#endif
Pali Roháre0c6d252023-03-29 21:03:32 +0200113#ifdef BOOT_FROM_UART
114 if (BOOT_FROM_UART(boot_device))
Marek Behúnee76b4a2021-08-16 15:19:37 +0200115 return BOOT_DEVICE_UART;
Pali Roháre0c6d252023-03-29 21:03:32 +0200116#endif
Marek Behúnee76b4a2021-08-16 15:19:37 +0200117#ifdef BOOT_FROM_SATA
Pali Roháre0c6d252023-03-29 21:03:32 +0200118 if (BOOT_FROM_SATA(boot_device))
Marek Behúnee76b4a2021-08-16 15:19:37 +0200119 return BOOT_DEVICE_SATA;
120#endif
Pali Roháre0c6d252023-03-29 21:03:32 +0200121#ifdef BOOT_FROM_SPI
122 if (BOOT_FROM_SPI(boot_device))
Marek Behúnee76b4a2021-08-16 15:19:37 +0200123 return BOOT_DEVICE_SPI;
Pali Roháre0c6d252023-03-29 21:03:32 +0200124#endif
125 return BOOT_DEVICE_BOOTROM;
Marek Behúnee76b4a2021-08-16 15:19:37 +0200126}
127
Stefan Roese93e6bf42014-10-22 12:13:17 +0200128#if defined(CONFIG_DISPLAY_CPUINFO)
Stefan Roese2a539c82015-12-21 12:36:40 +0100129
Stefan Roese479f9af2016-02-10 07:23:00 +0100130#if defined(CONFIG_ARMADA_375)
131/* SAR frequency values for Armada 375 */
132static const struct sar_freq_modes sar_freq_tab[] = {
133 { 0, 0x0, 266, 133, 266 },
134 { 1, 0x0, 333, 167, 167 },
135 { 2, 0x0, 333, 167, 222 },
136 { 3, 0x0, 333, 167, 333 },
137 { 4, 0x0, 400, 200, 200 },
138 { 5, 0x0, 400, 200, 267 },
139 { 6, 0x0, 400, 200, 400 },
140 { 7, 0x0, 500, 250, 250 },
141 { 8, 0x0, 500, 250, 334 },
142 { 9, 0x0, 500, 250, 500 },
143 { 10, 0x0, 533, 267, 267 },
144 { 11, 0x0, 533, 267, 356 },
145 { 12, 0x0, 533, 267, 533 },
146 { 13, 0x0, 600, 300, 300 },
147 { 14, 0x0, 600, 300, 400 },
148 { 15, 0x0, 600, 300, 600 },
149 { 16, 0x0, 666, 333, 333 },
150 { 17, 0x0, 666, 333, 444 },
151 { 18, 0x0, 666, 333, 666 },
152 { 19, 0x0, 800, 400, 267 },
153 { 20, 0x0, 800, 400, 400 },
154 { 21, 0x0, 800, 400, 534 },
155 { 22, 0x0, 900, 450, 300 },
156 { 23, 0x0, 900, 450, 450 },
157 { 24, 0x0, 900, 450, 600 },
158 { 25, 0x0, 1000, 500, 500 },
159 { 26, 0x0, 1000, 500, 667 },
160 { 27, 0x0, 1000, 333, 500 },
161 { 28, 0x0, 400, 400, 400 },
162 { 29, 0x0, 1100, 550, 550 },
163 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
164};
165#elif defined(CONFIG_ARMADA_38X)
Stefan Roesec03a2132016-01-07 14:03:11 +0100166/* SAR frequency values for Armada 38x */
Stefan Roese32139c32016-01-07 14:04:51 +0100167static const struct sar_freq_modes sar_freq_tab[] = {
Chris Packham5ccd14e2017-09-05 17:03:26 +1200168 { 0x0, 0x0, 666, 333, 333 },
169 { 0x2, 0x0, 800, 400, 400 },
170 { 0x4, 0x0, 1066, 533, 533 },
171 { 0x6, 0x0, 1200, 600, 600 },
172 { 0x8, 0x0, 1332, 666, 666 },
173 { 0xc, 0x0, 1600, 800, 800 },
174 { 0x10, 0x0, 1866, 933, 933 },
175 { 0x13, 0x0, 2000, 1000, 933 },
176 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
Stefan Roese2a539c82015-12-21 12:36:40 +0100177};
Chris Packhama8f845e2019-04-11 22:22:50 +1200178#elif defined(CONFIG_ARMADA_MSYS)
179static const struct sar_freq_modes sar_freq_tab[] = {
180 { 0x0, 0x0, 400, 400, 400 },
181 { 0x2, 0x0, 667, 333, 667 },
182 { 0x3, 0x0, 800, 400, 800 },
183 { 0x5, 0x0, 800, 400, 800 },
184 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
185};
Stefan Roese2a539c82015-12-21 12:36:40 +0100186#else
Stefan Roesec03a2132016-01-07 14:03:11 +0100187/* SAR frequency values for Armada XP */
Stefan Roese32139c32016-01-07 14:04:51 +0100188static const struct sar_freq_modes sar_freq_tab[] = {
Stefan Roese2a539c82015-12-21 12:36:40 +0100189 { 0xa, 0x5, 800, 400, 400 },
190 { 0x1, 0x5, 1066, 533, 533 },
191 { 0x2, 0x5, 1200, 600, 600 },
192 { 0x2, 0x9, 1200, 600, 400 },
193 { 0x3, 0x5, 1333, 667, 667 },
194 { 0x4, 0x5, 1500, 750, 750 },
195 { 0x4, 0x9, 1500, 750, 500 },
196 { 0xb, 0x9, 1600, 800, 533 },
197 { 0xb, 0xa, 1600, 800, 640 },
198 { 0xb, 0x5, 1600, 800, 800 },
199 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
200};
201#endif
202
203void get_sar_freq(struct sar_freq_modes *sar_freq)
204{
205 u32 val;
206 u32 freq;
207 int i;
208
Chris Packhama8f845e2019-04-11 22:22:50 +1200209#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
Tom Rinid7b93782022-12-04 10:13:41 -0500210 val = readl(CFG_SAR2_REG); /* SAR - Sample At Reset */
Stefan Roese479f9af2016-02-10 07:23:00 +0100211#else
Tom Rini253b6a22022-12-04 10:13:42 -0500212 val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */
Stefan Roese479f9af2016-02-10 07:23:00 +0100213#endif
Stefan Roese2a539c82015-12-21 12:36:40 +0100214 freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
Stefan Roese479f9af2016-02-10 07:23:00 +0100215#if defined(SAR2_CPU_FREQ_MASK)
Stefan Roese2a539c82015-12-21 12:36:40 +0100216 /*
217 * Shift CPU0 clock frequency select bit from SAR2 register
218 * into correct position
219 */
Tom Rinid7b93782022-12-04 10:13:41 -0500220 freq |= ((readl(CFG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
Stefan Roese2a539c82015-12-21 12:36:40 +0100221 >> SAR2_CPU_FREQ_OFFS) << 3;
222#endif
223 for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
224 if (sar_freq_tab[i].val == freq) {
Chris Packhama8f845e2019-04-11 22:22:50 +1200225#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
Stefan Roese2a539c82015-12-21 12:36:40 +0100226 *sar_freq = sar_freq_tab[i];
227 return;
228#else
229 int k;
230 u8 ffc;
231
232 ffc = (val & SAR_FFC_FREQ_MASK) >>
233 SAR_FFC_FREQ_OFFS;
234 for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
235 if (sar_freq_tab[k].ffc == ffc) {
236 *sar_freq = sar_freq_tab[k];
237 return;
238 }
239 }
240 i = k;
241#endif
242 }
243 }
244
245 /* SAR value not found, return 0 for frequencies */
246 *sar_freq = sar_freq_tab[i - 1];
247}
248
Stefan Roese93e6bf42014-10-22 12:13:17 +0200249int print_cpuinfo(void)
250{
251 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
252 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
Stefan Roese2a539c82015-12-21 12:36:40 +0100253 struct sar_freq_modes sar_freq;
Stefan Roese93e6bf42014-10-22 12:13:17 +0200254
255 puts("SoC: ");
256
257 switch (devid) {
Phil Sutter22e553e2015-12-25 14:41:24 +0100258 case SOC_MV78230_ID:
259 puts("MV78230-");
260 break;
Stefan Roeseb158f372015-12-09 11:00:51 +0100261 case SOC_MV78260_ID:
262 puts("MV78260-");
263 break;
Stefan Roese93e6bf42014-10-22 12:13:17 +0200264 case SOC_MV78460_ID:
265 puts("MV78460-");
266 break;
Stefan Roese479f9af2016-02-10 07:23:00 +0100267 case SOC_88F6720_ID:
268 puts("MV88F6720-");
269 break;
Stefan Roese174d23e2015-04-25 06:29:51 +0200270 case SOC_88F6810_ID:
271 puts("MV88F6810-");
Stefan Roese93e6bf42014-10-22 12:13:17 +0200272 break;
Stefan Roese174d23e2015-04-25 06:29:51 +0200273 case SOC_88F6820_ID:
274 puts("MV88F6820-");
Stefan Roese93e6bf42014-10-22 12:13:17 +0200275 break;
Stefan Roese174d23e2015-04-25 06:29:51 +0200276 case SOC_88F6828_ID:
277 puts("MV88F6828-");
Stefan Roese93e6bf42014-10-22 12:13:17 +0200278 break;
Chris Packham348109d2017-09-04 17:38:31 +1200279 case SOC_98DX3236_ID:
280 puts("98DX3236-");
281 break;
282 case SOC_98DX3336_ID:
283 puts("98DX3336-");
284 break;
285 case SOC_98DX4251_ID:
286 puts("98DX4251-");
287 break;
Stefan Roese93e6bf42014-10-22 12:13:17 +0200288 default:
Stefan Roese174d23e2015-04-25 06:29:51 +0200289 puts("Unknown-");
Stefan Roese93e6bf42014-10-22 12:13:17 +0200290 break;
291 }
292
Pali Rohárfdf415c2022-07-15 10:13:12 +0200293 switch (devid) {
294 case SOC_MV78230_ID:
295 case SOC_MV78260_ID:
296 case SOC_MV78460_ID:
Stefan Roese174d23e2015-04-25 06:29:51 +0200297 switch (revid) {
298 case 1:
Stefan Roese2a539c82015-12-21 12:36:40 +0100299 puts("A0");
Stefan Roese174d23e2015-04-25 06:29:51 +0200300 break;
301 case 2:
Stefan Roese2a539c82015-12-21 12:36:40 +0100302 puts("B0");
Stefan Roese174d23e2015-04-25 06:29:51 +0200303 break;
304 default:
Stefan Roese2a539c82015-12-21 12:36:40 +0100305 printf("?? (%x)", revid);
Stefan Roese174d23e2015-04-25 06:29:51 +0200306 break;
307 }
Pali Rohárfdf415c2022-07-15 10:13:12 +0200308 break;
Stefan Roese174d23e2015-04-25 06:29:51 +0200309
Pali Rohárfdf415c2022-07-15 10:13:12 +0200310 case SOC_88F6720_ID:
Stefan Roese479f9af2016-02-10 07:23:00 +0100311 switch (revid) {
312 case MV_88F67XX_A0_ID:
313 puts("A0");
314 break;
315 default:
316 printf("?? (%x)", revid);
317 break;
318 }
Pali Rohárfdf415c2022-07-15 10:13:12 +0200319 break;
Stefan Roese479f9af2016-02-10 07:23:00 +0100320
Pali Rohárfdf415c2022-07-15 10:13:12 +0200321 case SOC_88F6810_ID:
322 case SOC_88F6820_ID:
323 case SOC_88F6828_ID:
Stefan Roese174d23e2015-04-25 06:29:51 +0200324 switch (revid) {
325 case MV_88F68XX_Z1_ID:
Stefan Roese2a539c82015-12-21 12:36:40 +0100326 puts("Z1");
Stefan Roese174d23e2015-04-25 06:29:51 +0200327 break;
328 case MV_88F68XX_A0_ID:
Stefan Roese2a539c82015-12-21 12:36:40 +0100329 puts("A0");
Stefan Roese174d23e2015-04-25 06:29:51 +0200330 break;
Chris Packhamec4510b2018-11-28 10:32:00 +1300331 case MV_88F68XX_B0_ID:
332 puts("B0");
333 break;
Stefan Roese174d23e2015-04-25 06:29:51 +0200334 default:
Stefan Roese2a539c82015-12-21 12:36:40 +0100335 printf("?? (%x)", revid);
Stefan Roese174d23e2015-04-25 06:29:51 +0200336 break;
337 }
Pali Rohárfdf415c2022-07-15 10:13:12 +0200338 break;
Stefan Roese174d23e2015-04-25 06:29:51 +0200339
Pali Rohárfdf415c2022-07-15 10:13:12 +0200340 case SOC_98DX3236_ID:
341 case SOC_98DX3336_ID:
342 case SOC_98DX4251_ID:
Chris Packhama8f845e2019-04-11 22:22:50 +1200343 switch (revid) {
344 case 3:
345 puts("A0");
346 break;
347 case 4:
348 puts("A1");
349 break;
350 default:
351 printf("?? (%x)", revid);
352 break;
353 }
Pali Rohárfdf415c2022-07-15 10:13:12 +0200354 break;
355
356 default:
357 printf("?? (%x)", revid);
358 break;
Chris Packhama8f845e2019-04-11 22:22:50 +1200359 }
360
Stefan Roese2a539c82015-12-21 12:36:40 +0100361 get_sar_freq(&sar_freq);
362 printf(" at %d MHz\n", sar_freq.p_clk);
363
Stefan Roese93e6bf42014-10-22 12:13:17 +0200364 return 0;
365}
366#endif /* CONFIG_DISPLAY_CPUINFO */
367
368/*
369 * This function initialize Controller DRAM Fastpath windows.
370 * It takes the CS size information from the 0x1500 scratch registers
371 * and sets the correct windows sizes and base addresses accordingly.
372 *
373 * These values are set in the scratch registers by the Marvell
Chris Packham1cd77b02018-12-14 16:27:57 +1300374 * DDR3 training code, which is executed by the SPL before the
375 * main payload (U-Boot) is executed.
Stefan Roese93e6bf42014-10-22 12:13:17 +0200376 */
377static void update_sdram_window_sizes(void)
378{
379 u64 base = 0;
380 u32 size, temp;
381 int i;
382
383 for (i = 0; i < SDRAM_MAX_CS; i++) {
384 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
385 if (size != 0) {
386 size |= ~(SDRAM_ADDR_MASK);
387
388 /* Set Base Address */
389 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
390 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
391
392 /*
393 * Check if out of max window size and resize
394 * the window
395 */
396 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
397 ~(SDRAM_ADDR_MASK)) | 1;
398 temp |= (size & SDRAM_ADDR_MASK);
399 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
400
401 base += ((u64)size + 1);
402 } else {
403 /*
404 * Disable window if not used, otherwise this
405 * leads to overlapping enabled windows with
406 * pretty strange results
407 */
408 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
409 }
410 }
411}
412
413#ifdef CONFIG_ARCH_CPU_INIT
Stefan Roesef43d3232015-07-22 18:26:13 +0200414#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
415#define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
416#define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
417 (((addr) & 0xF) << 6))
418#define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
419 (((reg) & 0xF) << 2))
420
421static void setup_usb_phys(void)
422{
423 int dev;
424
425 /*
426 * USB PLL init
427 */
428
429 /* Setup PLL frequency */
430 /* USB REF frequency = 25 MHz */
431 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
432
433 /* Power up PLL and PHY channel */
Stefan Roese0b1d5372015-12-04 13:08:34 +0100434 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
Stefan Roesef43d3232015-07-22 18:26:13 +0200435
436 /* Assert VCOCAL_START */
Stefan Roese0b1d5372015-12-04 13:08:34 +0100437 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
Stefan Roesef43d3232015-07-22 18:26:13 +0200438
439 mdelay(1);
440
441 /*
442 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
443 */
444
445 for (dev = 0; dev < 3; dev++) {
Stefan Roese0b1d5372015-12-04 13:08:34 +0100446 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
Stefan Roesef43d3232015-07-22 18:26:13 +0200447
448 /* Assert REG_RCAL_START in channel REG 1 */
Stefan Roese0b1d5372015-12-04 13:08:34 +0100449 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
Stefan Roesef43d3232015-07-22 18:26:13 +0200450 udelay(40);
Stefan Roese0b1d5372015-12-04 13:08:34 +0100451 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
Stefan Roesef43d3232015-07-22 18:26:13 +0200452 }
453}
Kevin Smith1ddff022015-05-18 16:09:44 +0000454
Stefan Roesee7c72282015-12-03 12:39:45 +0100455/*
456 * This function is not called from the SPL U-Boot version
457 */
Stefan Roese93e6bf42014-10-22 12:13:17 +0200458int arch_cpu_init(void)
459{
Stefan Roese93e6bf42014-10-22 12:13:17 +0200460 /*
461 * We need to call mvebu_mbus_probe() before calling
462 * update_sdram_window_sizes() as it disables all previously
463 * configured mbus windows and then configures them as
464 * required for U-Boot. Calling update_sdram_window_sizes()
465 * without this configuration will not work, as the internal
466 * registers can't be accessed reliably because of potenial
467 * double mapping.
468 * After updating the SDRAM access windows we need to call
469 * mvebu_mbus_probe() again, as this now correctly configures
470 * the SDRAM areas that are later used by the MVEBU drivers
471 * (e.g. USB, NETA).
472 */
473
474 /*
475 * First disable all windows
476 */
477 mvebu_mbus_probe(NULL, 0);
478
Pali Rohárfdf415c2022-07-15 10:13:12 +0200479 if (IS_ENABLED(CONFIG_ARMADA_XP)) {
Stefan Roese174d23e2015-04-25 06:29:51 +0200480 /*
481 * Now the SDRAM access windows can be reconfigured using
482 * the information in the SDRAM scratch pad registers
483 */
484 update_sdram_window_sizes();
485 }
Stefan Roese93e6bf42014-10-22 12:13:17 +0200486
487 /*
488 * Finally the mbus windows can be configured with the
489 * updated SDRAM sizes
490 */
491 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
492
Pali Rohárfdf415c2022-07-15 10:13:12 +0200493 if (IS_ENABLED(CONFIG_ARMADA_XP)) {
Stefan Roesebadccc32015-07-16 10:40:05 +0200494 /* Enable GBE0, GBE1, LCD and NFC PUP */
495 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
496 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
497 NAND_PUP_EN | SPI_PUP_EN);
Stefan Roesef43d3232015-07-22 18:26:13 +0200498
499 /* Configure USB PLL and PHYs on AXP */
500 setup_usb_phys();
Stefan Roesebadccc32015-07-16 10:40:05 +0200501 }
502
503 /* Enable NAND and NAND arbiter */
504 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
505
Stefan Roese8ac6dab2015-07-01 13:28:39 +0200506 /* Disable MBUS error propagation */
507 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
508
Stefan Roese93e6bf42014-10-22 12:13:17 +0200509 return 0;
510}
511#endif /* CONFIG_ARCH_CPU_INIT */
512
Stefan Roesebadccc32015-07-16 10:40:05 +0200513u32 mvebu_get_nand_clock(void)
514{
Chris Packham460086e2016-08-22 12:38:39 +1200515 u32 reg;
516
Pali Rohárfdf415c2022-07-15 10:13:12 +0200517 if (IS_ENABLED(CONFIG_ARMADA_38X))
Chris Packham460086e2016-08-22 12:38:39 +1200518 reg = MVEBU_DFX_DIV_CLK_CTRL(1);
Pali Rohárfdf415c2022-07-15 10:13:12 +0200519 else if (IS_ENABLED(CONFIG_ARMADA_MSYS))
Chris Packham7ce3f8c2019-04-11 22:22:51 +1200520 reg = MVEBU_DFX_DIV_CLK_CTRL(8);
Chris Packham460086e2016-08-22 12:38:39 +1200521 else
522 reg = MVEBU_CORE_DIV_CLK_CTRL(1);
523
Stefan Roesebadccc32015-07-16 10:40:05 +0200524 return CONFIG_SYS_MVEBU_PLL_CLOCK /
Chris Packham460086e2016-08-22 12:38:39 +1200525 ((readl(reg) &
Stefan Roesebadccc32015-07-16 10:40:05 +0200526 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
527}
528
Pierre Bourdonb9af62d2019-04-11 04:56:58 +0200529#if defined(CONFIG_MMC_SDHCI_MV) && !defined(CONFIG_DM_MMC)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900530int board_mmc_init(struct bd_info *bis)
Stefan Roesed3e34732015-06-29 14:58:10 +0200531{
532 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
533 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
534
535 return 0;
536}
537#endif
538
Stefan Roesebb1c0bd2015-06-29 14:58:13 +0200539#define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
540#define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
541
542#define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
543#define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
544#define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
545
546static void ahci_mvebu_mbus_config(void __iomem *base)
547{
548 const struct mbus_dram_target_info *dram;
549 int i;
550
Baruch Siach2179c772019-05-16 13:03:57 +0300551 /* mbus is not initialized in SPL; keep the ROM settings */
552 if (IS_ENABLED(CONFIG_SPL_BUILD))
553 return;
554
Stefan Roesebb1c0bd2015-06-29 14:58:13 +0200555 dram = mvebu_mbus_dram_info();
556
557 for (i = 0; i < 4; i++) {
558 writel(0, base + AHCI_WINDOW_CTRL(i));
559 writel(0, base + AHCI_WINDOW_BASE(i));
560 writel(0, base + AHCI_WINDOW_SIZE(i));
561 }
562
563 for (i = 0; i < dram->num_cs; i++) {
564 const struct mbus_dram_window *cs = dram->cs + i;
565
566 writel((cs->mbus_attr << 8) |
567 (dram->mbus_dram_target_id << 4) | 1,
568 base + AHCI_WINDOW_CTRL(i));
569 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
570 writel(((cs->size - 1) & 0xffff0000),
571 base + AHCI_WINDOW_SIZE(i));
572 }
573}
574
575static void ahci_mvebu_regret_option(void __iomem *base)
576{
577 /*
578 * Enable the regret bit to allow the SATA unit to regret a
579 * request that didn't receive an acknowlegde and avoid a
580 * deadlock
581 */
582 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
583 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
584}
585
Baruch Siachb590a142019-03-24 13:27:43 +0200586int board_ahci_enable(void)
Stefan Roesebb1c0bd2015-06-29 14:58:13 +0200587{
Stefan Roesebb1c0bd2015-06-29 14:58:13 +0200588 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
589 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
Baruch Siachb590a142019-03-24 13:27:43 +0200590
591 return 0;
592}
593
Jon Nettleton86502322017-11-06 10:33:20 +0200594#ifdef CONFIG_USB_XHCI_MVEBU
595#define USB3_MAX_WINDOWS 4
596#define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
597#define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
598
599static void xhci_mvebu_mbus_config(void __iomem *base,
600 const struct mbus_dram_target_info *dram)
601{
602 int i;
603
604 for (i = 0; i < USB3_MAX_WINDOWS; i++) {
605 writel(0, base + USB3_WIN_CTRL(i));
606 writel(0, base + USB3_WIN_BASE(i));
607 }
608
609 for (i = 0; i < dram->num_cs; i++) {
610 const struct mbus_dram_window *cs = dram->cs + i;
611
612 /* Write size, attributes and target id to control register */
613 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
614 (dram->mbus_dram_target_id << 4) | 1,
615 base + USB3_WIN_CTRL(i));
616
617 /* Write base address to base register */
618 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
619 }
620}
621
622int board_xhci_enable(fdt_addr_t base)
623{
624 const struct mbus_dram_target_info *dram;
625
Johan Jonker511a0472023-03-13 01:32:57 +0100626 printf("MVEBU XHCI INIT controller @ 0x%llx\n", (fdt64_t)base);
Jon Nettleton86502322017-11-06 10:33:20 +0200627
628 dram = mvebu_mbus_dram_info();
629 xhci_mvebu_mbus_config((void __iomem *)base, dram);
630
631 return 0;
632}
633#endif
634
Stefan Roese93e6bf42014-10-22 12:13:17 +0200635void enable_caches(void)
636{
Stefan Roese7a4a5ba2015-04-25 06:29:55 +0200637 /* Avoid problem with e.g. neta ethernet driver */
638 invalidate_dcache_all();
639
Stefan Roesedafe60f2016-02-10 09:18:46 +0100640 /*
641 * Armada 375 still has some problems with d-cache enabled in the
642 * ethernet driver (mvpp2). So lets keep the d-cache disabled
643 * until this is solved.
644 */
Pali Rohárb94cb132022-09-08 16:06:50 +0200645 if (!IS_ENABLED(CONFIG_ARMADA_375)) {
Stefan Roesedafe60f2016-02-10 09:18:46 +0100646 /* Enable D-cache. I-cache is already enabled in start.S */
647 dcache_enable();
648 }
Stefan Roese93e6bf42014-10-22 12:13:17 +0200649}
Stefan Roese479a9772015-12-03 12:39:45 +0100650
651void v7_outer_cache_enable(void)
652{
Pali Rohár2100c4d2022-09-08 16:06:53 +0200653 struct pl310_regs *const pl310 =
Tom Rini6a5dccc2022-11-16 13:10:41 -0500654 (struct pl310_regs *)CFG_SYS_PL310_BASE;
Pali Rohár2100c4d2022-09-08 16:06:53 +0200655
656 /* The L2 cache is already disabled at this point */
657
658 /*
659 * For now L2 cache will be enabled only for Armada XP and Armada 38x.
660 * It can be enabled also for other SoCs after testing that it works fine.
661 */
662 if (!IS_ENABLED(CONFIG_ARMADA_XP) && !IS_ENABLED(CONFIG_ARMADA_38X))
663 return;
664
Pali Rohárfdf415c2022-07-15 10:13:12 +0200665 if (IS_ENABLED(CONFIG_ARMADA_XP)) {
Stefan Roese479a9772015-12-03 12:39:45 +0100666 u32 u;
667
668 /*
669 * For Aurora cache in no outer mode, enable via the CP15
670 * coprocessor broadcasting of cache commands to L2.
671 */
672 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
673 u |= BIT(8); /* Set the FW bit */
674 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
675
676 isb();
Stefan Roese479a9772015-12-03 12:39:45 +0100677 }
Pali Rohár2100c4d2022-09-08 16:06:53 +0200678
679 /* Enable the L2 cache */
680 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
Stefan Roese479a9772015-12-03 12:39:45 +0100681}
Stefan Roese77b299c2015-12-14 12:31:48 +0100682
683void v7_outer_cache_disable(void)
684{
685 struct pl310_regs *const pl310 =
Tom Rini6a5dccc2022-11-16 13:10:41 -0500686 (struct pl310_regs *)CFG_SYS_PL310_BASE;
Stefan Roese77b299c2015-12-14 12:31:48 +0100687
688 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
689}