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git01.mediatek.com / filogic / uboot / c69b30942c6800cc0d481b1e686d9e85e201e062 / . / arch / powerpc / cpu / ppc4xx / usb.c
blob: 16b44ccea0696425204924698c56d27f2eda41fb [file] [log] [blame]
Markus Klotzbuecherae950872007-06-06 11:49:43 +0200[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Markus Klotzbuecherae950872007-06-06 11:49:43 +0200[diff] [blame]6 */
7
8#include <common.h>
9
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]10#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
Markus Klotzbuecherae950872007-06-06 11:49:43 +0200[diff] [blame]11
Matthias Fuchsc3dddd62007-11-09 15:37:23 +0100[diff] [blame]12#ifdef CONFIG_4xx_DCACHE
13#include <asm/mmu.h>
14DECLARE_GLOBAL_DATA_PTR;
15#endif
16
Stefan Roese75a3d5d2007-08-14 16:36:29 +0200[diff] [blame]17int usb_cpu_init(void)
Markus Klotzbuecherae950872007-06-06 11:49:43 +0200[diff] [blame]18{
Matthias Fuchsc3dddd62007-11-09 15:37:23 +0100[diff] [blame]19#ifdef CONFIG_4xx_DCACHE
20 /* disable cache */
21 change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
22#endif
Markus Klotzbuecherae950872007-06-06 11:49:43 +0200[diff] [blame]23
Markus Klotzbuecherae950872007-06-06 11:49:43 +0200[diff] [blame]24 return 0;
25}
26
Stefan Roese75a3d5d2007-08-14 16:36:29 +0200[diff] [blame]27int usb_cpu_stop(void)
Markus Klotzbuecherae950872007-06-06 11:49:43 +0200[diff] [blame]28{
Matthias Fuchsc3dddd62007-11-09 15:37:23 +0100[diff] [blame]29#ifdef CONFIG_4xx_DCACHE
30 /* enable cache */
31 change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
32#endif
Markus Klotzbuecherae950872007-06-06 11:49:43 +0200[diff] [blame]33 return 0;
34}
35
Stefan Roese75a3d5d2007-08-14 16:36:29 +0200[diff] [blame]36int usb_cpu_init_fail(void)
Markus Klotzbuecherae950872007-06-06 11:49:43 +0200[diff] [blame]37{
Matthias Fuchsc3dddd62007-11-09 15:37:23 +0100[diff] [blame]38#ifdef CONFIG_4xx_DCACHE
39 /* enable cache */
40 change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
41#endif
Markus Klotzbuecherae950872007-06-06 11:49:43 +0200[diff] [blame]42 return 0;
43}
44
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]45#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */