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git01.mediatek.com / filogic / uboot / c47e207625beb3bf704d27b6abf502a703ce6bbf / . / arch / m68k / include / asm / immap.h
blob: ead62cd03871ff701d2e596fe1961ea7593f5e60 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]2/*
3 * ColdFire Internal Memory Map and Defines
4 *
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]5 * Copyright 2004-2012 Freescale Semiconductor, Inc.
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]7 */
8
9#ifndef __IMMAP_H
10#define __IMMAP_H
Stefan Roesef1110122007-07-16 13:11:12 +0200[diff] [blame]11
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]12#if defined(CONFIG_MCF520x)
13#include <asm/immap_520x.h>
14#include <asm/m520x.h>
15
16#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
17#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
18
19/* Timer */
20#ifdef CONFIG_MCFTMR
21#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
22#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
23#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
24#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
25#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
26#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
27#define CONFIG_SYS_TMRINTR_PRI (6)
28#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
29#endif
30
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]31#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
32#define CONFIG_SYS_NUM_IRQS (128)
33#endif /* CONFIG_M520x */
34
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]35#ifdef CONFIG_M5235
36#include <asm/immap_5235.h>
37#include <asm/m5235.h>
38
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]39#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
40#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]41
42/* Timer */
43#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]44#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
45#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
46#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
47#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
48#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
49#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
50#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
51#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]52#endif
53
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]54#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
55#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]56#endif /* CONFIG_M5235 */
57
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]58#ifdef CONFIG_M5249
59#include <asm/immap_5249.h>
60#include <asm/m5249.h>
61
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]62#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]63
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]64#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
65#define CONFIG_SYS_NUM_IRQS (64)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]66
67/* Timer */
68#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]69#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
70#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
71#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
72#define CONFIG_SYS_TMRINTR_NO (31)
73#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
74#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
75#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
76#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]77#endif
78#endif /* CONFIG_M5249 */
79
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]80#ifdef CONFIG_M5253
81#include <asm/immap_5253.h>
82#include <asm/m5249.h>
83#include <asm/m5253.h>
84
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]85#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]86
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]87#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
88#define CONFIG_SYS_NUM_IRQS (64)
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]89
90/* Timer */
91#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]92#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
93#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
94#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
95#define CONFIG_SYS_TMRINTR_NO (27)
96#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
97#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
98#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
99#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]100#endif
101#endif /* CONFIG_M5253 */
102
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]103#ifdef CONFIG_M5271
104#include <asm/immap_5271.h>
105#include <asm/m5271.h>
106
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]107#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
108#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]109
110/* Timer */
111#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]112#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
113#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
114#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
115#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
116#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
117#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
Richard Retanubun0dd94312009-03-26 15:26:01 -0400[diff] [blame]118#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]119#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]120#endif
121
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]122#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
123#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]124#endif /* CONFIG_M5271 */
125
126#ifdef CONFIG_M5272
127#include <asm/immap_5272.h>
128#include <asm/m5272.h>
129
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]130#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
131#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]132
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]133#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
134#define CONFIG_SYS_NUM_IRQS (64)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]135
136/* Timer */
137#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]138#define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0)
139#define CONFIG_SYS_TMR_BASE (MMAP_TMR3)
140#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
141#define CONFIG_SYS_TMRINTR_NO (INT_TMR3)
142#define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24)
143#define CONFIG_SYS_TMRINTR_PEND (0)
144#define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
145#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]146#endif
147#endif /* CONFIG_M5272 */
148
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]149#ifdef CONFIG_M5275
150#include <asm/immap_5275.h>
151#include <asm/m5275.h>
152
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]153#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
154#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
155#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]156
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]157#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
158#define CONFIG_SYS_NUM_IRQS (192)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]159
160/* Timer */
161#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]162#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
163#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
164#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
165#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
166#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
167#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
168#define CONFIG_SYS_TMRINTR_PRI (0x1E)
169#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]170#endif
171#endif /* CONFIG_M5275 */
172
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]173#ifdef CONFIG_M5282
174#include <asm/immap_5282.h>
175#include <asm/m5282.h>
176
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]177#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
178#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]179
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]180#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
181#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]182
183/* Timer */
184#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]185#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
186#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
187#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
188#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
189#define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
190#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
191#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
192#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]193#endif
194#endif /* CONFIG_M5282 */
195
angelo@sysam.itbb4ba2c2015-02-12 01:40:00 +0100[diff] [blame]196#ifdef CONFIG_M5307
197#include <asm/immap_5307.h>
198#include <asm/m5307.h>
199
200#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
201 (CONFIG_SYS_UART_PORT * 0x40))
202#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
203#define CONFIG_SYS_NUM_IRQS (64)
204
205/* Timer */
206#ifdef CONFIG_MCFTMR
207#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
208#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
209#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \
210 (CONFIG_SYS_INTR_BASE))->ipr)
211#define CONFIG_SYS_TMRINTR_NO (31)
212#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
213#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
214#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
215 MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
216#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
217#endif
218#endif /* CONFIG_M5307 */
219
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]220#if defined(CONFIG_MCF5301x)
221#include <asm/immap_5301x.h>
222#include <asm/m5301x.h>
223
224#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
225#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
226#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
227
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]228/* Timer */
229#ifdef CONFIG_MCFTMR
230#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
231#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
232#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
233#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
234#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
235#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
236#define CONFIG_SYS_TMRINTR_PRI (6)
237#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
238#endif
239
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]240#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
241#define CONFIG_SYS_NUM_IRQS (128)
242#endif /* CONFIG_M5301x */
243
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600[diff] [blame]244#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]245#include <asm/immap_5329.h>
246#include <asm/m5329.h>
247
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]248#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
249#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]250
251/* Timer */
252#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]253#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
254#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
255#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
256#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
257#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
258#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
259#define CONFIG_SYS_TMRINTR_PRI (6)
260#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]261#endif
262
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]263#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
264#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600[diff] [blame]265#endif /* CONFIG_M5329 && CONFIG_M5373 */
Stefan Roesef1110122007-07-16 13:11:12 +0200[diff] [blame]266
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]267#if defined(CONFIG_M54418)
268#include <asm/immap_5441x.h>
269#include <asm/m5441x.h>
270
271#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
272#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
273
274#if (CONFIG_SYS_UART_PORT < 4)
275#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
276 (CONFIG_SYS_UART_PORT * 0x4000))
277#else
278#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
279 ((CONFIG_SYS_UART_PORT - 4) * 0x4000))
280#endif
281
282#define MMAP_DSPI MMAP_DSPI0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]283
284/* Timer */
285#ifdef CONFIG_MCFTMR
286#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
287#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
288#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
289#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
290#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
291#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
292#define CONFIG_SYS_TMRINTR_PRI (6)
293#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
294#endif
295
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]296#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
Angelo Dureghelloe2f93932018-02-04 21:13:12 +0100[diff] [blame]297#define CONFIG_SYS_NUM_IRQS (192)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]298
299#endif /* CONFIG_M54418 */
300
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]301#ifdef CONFIG_M547x
302#include <asm/immap_547x_8x.h>
303#include <asm/m547x_8x.h>
304
305#ifdef CONFIG_FSLDMAFEC
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]306#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
307#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]308
309#define FEC0_RX_TASK 0
310#define FEC0_TX_TASK 1
311#define FEC0_RX_PRIORITY 6
312#define FEC0_TX_PRIORITY 7
313#define FEC0_RX_INIT 16
314#define FEC0_TX_INIT 17
315#define FEC1_RX_TASK 2
316#define FEC1_TX_TASK 3
317#define FEC1_RX_PRIORITY 6
318#define FEC1_TX_PRIORITY 7
319#define FEC1_RX_INIT 30
320#define FEC1_TX_INIT 31
321#endif
322
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]323#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]324
325#ifdef CONFIG_SLTTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]326#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
327#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
328#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
329#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
330#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
331#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
332#define CONFIG_SYS_TMRINTR_PRI (0x1E)
333#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]334#endif
335
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]336#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
337#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]338
339#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]340#define CONFIG_SYS_PCI_BAR0 (0x40000000)
341#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
342#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
343#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]344#endif
345#endif /* CONFIG_M547x */
346
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]347#endif /* __IMMAP_H */