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git01.mediatek.com / filogic / uboot / ef73783a555957abe90cb17d0a61ceca89194fa7 / . / arch / arm / cpu / armv7 / mx6 / ddr.c
blob: 1ab69f63c8507f0e51d90d1253bd016a61e55694 [file] [log] [blame]
Tim Harvey8ab871b2014-06-02 16:13:23 -0700[diff] [blame]1/*
2 * Copyright (C) 2014 Gateworks Corporation
3 * Author: Tim Harvey <tharvey@gateworks.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <linux/types.h>
10#include <asm/arch/mx6-ddr.h>
11#include <asm/arch/sys_proto.h>
12#include <asm/io.h>
13#include <asm/types.h>
14
15#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
16/* Configure MX6DQ mmdc iomux */
17void mx6dq_dram_iocfg(unsigned width,
18 const struct mx6dq_iomux_ddr_regs *ddr,
19 const struct mx6dq_iomux_grp_regs *grp)
20{
21 volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
22 volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
23
24 mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
25 mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
26
27 /* DDR IO Type */
28 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
29 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
30
31 /* Clock */
32 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
33 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
34
35 /* Address */
36 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
37 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
38 mx6_grp_iomux->grp_addds = grp->grp_addds;
39
40 /* Control */
41 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
42 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
43 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
44 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
45 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
46 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
47 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
48
49 /* Data Strobes */
50 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
51 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
52 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
53 if (width >= 32) {
54 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
55 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
56 }
57 if (width >= 64) {
58 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
59 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
60 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
61 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
62 }
63
64 /* Data */
65 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
66 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
67 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
68 if (width >= 32) {
69 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
70 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
71 }
72 if (width >= 64) {
73 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
74 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
75 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
76 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
77 }
78 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
79 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
80 if (width >= 32) {
81 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
82 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
83 }
84 if (width >= 64) {
85 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
86 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
87 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
88 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
89 }
90}
91#endif
92
93#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
94/* Configure MX6SDL mmdc iomux */
95void mx6sdl_dram_iocfg(unsigned width,
96 const struct mx6sdl_iomux_ddr_regs *ddr,
97 const struct mx6sdl_iomux_grp_regs *grp)
98{
99 volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
100 volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
101
102 mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
103 mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
104
105 /* DDR IO Type */
106 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
107 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
108
109 /* Clock */
110 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
111 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
112
113 /* Address */
114 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
115 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
116 mx6_grp_iomux->grp_addds = grp->grp_addds;
117
118 /* Control */
119 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
120 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
121 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
122 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
123 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
124 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
125 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
126
127 /* Data Strobes */
128 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
129 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
130 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
131 if (width >= 32) {
132 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
133 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
134 }
135 if (width >= 64) {
136 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
137 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
138 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
139 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
140 }
141
142 /* Data */
143 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
144 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
145 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
146 if (width >= 32) {
147 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
148 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
149 }
150 if (width >= 64) {
151 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
152 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
153 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
154 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
155 }
156 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
157 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
158 if (width >= 32) {
159 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
160 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
161 }
162 if (width >= 64) {
163 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
164 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
165 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
166 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
167 }
168}
169#endif
170
171/*
172 * Configure mx6 mmdc registers based on:
173 * - board-specific memory configuration
174 * - board-specific calibration data
175 * - ddr3 chip details
176 *
177 * The various calculations here are derived from the Freescale
178 * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
179 * configuration registers based on memory system and memory chip parameters.
180 *
181 * The defaults here are those which were specified in the spreadsheet.
182 * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
183 * section titled MMDC initialization
184 */
185#define MR(val, ba, cmd, cs1) \
186 ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
187void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
188 const struct mx6_mmdc_calibration *c,
189 const struct mx6_ddr3_cfg *m)
190{
191 volatile struct mmdc_p_regs *mmdc0;
192 volatile struct mmdc_p_regs *mmdc1;
193 u32 reg;
194 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
195 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
196 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
197 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
198 u16 CS0_END;
199 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
Marek Vasut4a463602014-08-04 01:47:10 +0200[diff] [blame]200 u8 coladdr;
Tim Harvey8ab871b2014-06-02 16:13:23 -0700[diff] [blame]201 int clkper; /* clock period in picoseconds */
202 int clock; /* clock freq in mHz */
203 int cs;
204
205 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
206 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
207
208 /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
209 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
210 clock = 528;
211 tcwl = 4;
212 }
213 /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
214 else {
215 clock = 400;
216 tcwl = 3;
217 }
218 clkper = (1000*1000)/clock; /* ps */
219 todtlon = tcwl;
220 taxpd = tcwl;
221 tanpd = tcwl;
222 tcwl = tcwl;
223
224 switch (m->density) {
225 case 1: /* 1Gb per chip */
226 trfc = DIV_ROUND_UP(110000, clkper) - 1;
227 txs = DIV_ROUND_UP(120000, clkper) - 1;
228 break;
229 case 2: /* 2Gb per chip */
230 trfc = DIV_ROUND_UP(160000, clkper) - 1;
231 txs = DIV_ROUND_UP(170000, clkper) - 1;
232 break;
233 case 4: /* 4Gb per chip */
234 trfc = DIV_ROUND_UP(260000, clkper) - 1;
235 txs = DIV_ROUND_UP(270000, clkper) - 1;
236 break;
237 case 8: /* 8Gb per chip */
238 trfc = DIV_ROUND_UP(350000, clkper) - 1;
239 txs = DIV_ROUND_UP(360000, clkper) - 1;
240 break;
241 default:
242 /* invalid density */
243 printf("invalid chip density\n");
244 hang();
245 break;
246 }
247 txpr = txs;
248
249 switch (m->mem_speed) {
250 case 800:
251 txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
252 tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
253 if (m->pagesz == 1) {
254 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
255 trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
256 } else {
257 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
258 trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
259 }
260 break;
261 case 1066:
262 txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
263 tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
264 if (m->pagesz == 1) {
265 tfaw = DIV_ROUND_UP(37500, clkper) - 1;
266 trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
267 } else {
268 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
269 trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
270 }
271 break;
272 case 1333:
273 txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
274 tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
275 if (m->pagesz == 1) {
276 tfaw = DIV_ROUND_UP(30000, clkper) - 1;
277 trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
278 } else {
279 tfaw = DIV_ROUND_UP(45000, clkper) - 1;
280 trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
281 }
282 break;
283 case 1600:
284 txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
285 tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;
286 if (m->pagesz == 1) {
287 tfaw = DIV_ROUND_UP(30000, clkper) - 1;
288 trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
289 } else {
290 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
291 trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
292 }
293 break;
294 default:
295 printf("invalid memory speed\n");
296 hang();
297 break;
298 }
299 txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;
300 tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;
301 tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
302 tcksrx = tcksre;
303 taonpd = DIV_ROUND_UP(2000, clkper) - 1;
304 taofpd = taonpd;
305 trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
306 trcd = trp;
307 trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
308 tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
309 twr = DIV_ROUND_UP(15000, clkper) - 1;
310 tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
311 twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
312 trtp = twtr;
313 CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;
314 debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
315 debug("clock: %dMHz (%d ps)\n", clock, clkper);
316 debug("memspd:%d\n", m->mem_speed);
317 debug("tcke=%d\n", tcke);
318 debug("tcksrx=%d\n", tcksrx);
319 debug("tcksre=%d\n", tcksre);
320 debug("taofpd=%d\n", taofpd);
321 debug("taonpd=%d\n", taonpd);
322 debug("todtlon=%d\n", todtlon);
323 debug("tanpd=%d\n", tanpd);
324 debug("taxpd=%d\n", taxpd);
325 debug("trfc=%d\n", trfc);
326 debug("txs=%d\n", txs);
327 debug("txp=%d\n", txp);
328 debug("txpdll=%d\n", txpdll);
329 debug("tfaw=%d\n", tfaw);
330 debug("tcl=%d\n", tcl);
331 debug("trcd=%d\n", trcd);
332 debug("trp=%d\n", trp);
333 debug("trc=%d\n", trc);
334 debug("tras=%d\n", tras);
335 debug("twr=%d\n", twr);
336 debug("tmrd=%d\n", tmrd);
337 debug("tcwl=%d\n", tcwl);
338 debug("tdllk=%d\n", tdllk);
339 debug("trtp=%d\n", trtp);
340 debug("twtr=%d\n", twtr);
341 debug("trrd=%d\n", trrd);
342 debug("txpr=%d\n", txpr);
343 debug("CS0_END=%d\n", CS0_END);
344 debug("ncs=%d\n", i->ncs);
345 debug("Rtt_wr=%d\n", i->rtt_wr);
346 debug("Rtt_nom=%d\n", i->rtt_nom);
347 debug("SRT=%d\n", m->SRT);
348 debug("tcl=%d\n", tcl);
349 debug("twr=%d\n", twr);
350
351 /*
352 * board-specific configuration:
353 * These values are determined empirically and vary per board layout
354 * see:
355 * appnote, ddr3 spreadsheet
356 */
357 mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;
358 mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;
359 mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;
360 mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;
361 mmdc0->mprddlctl = c->p0_mprddlctl;
362 mmdc0->mpwrdlctl = c->p0_mpwrdlctl;
363 if (i->dsize > 1) {
364 mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;
365 mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;
366 mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;
367 mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;
368 mmdc1->mprddlctl = c->p1_mprddlctl;
369 mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
370 }
371
372 /* Read data DQ Byte0-3 delay */
373 mmdc0->mprddqby0dl = (u32)0x33333333;
374 mmdc0->mprddqby1dl = (u32)0x33333333;
375 if (i->dsize > 0) {
376 mmdc0->mprddqby2dl = (u32)0x33333333;
377 mmdc0->mprddqby3dl = (u32)0x33333333;
378 }
379 if (i->dsize > 1) {
380 mmdc1->mprddqby0dl = (u32)0x33333333;
381 mmdc1->mprddqby1dl = (u32)0x33333333;
382 mmdc1->mprddqby2dl = (u32)0x33333333;
383 mmdc1->mprddqby3dl = (u32)0x33333333;
384 }
385
386 /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
387 reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;
388 mmdc0->mpodtctrl = reg;
389 if (i->dsize > 1)
390 mmdc1->mpodtctrl = reg;
391
392 /* complete calibration */
393 reg = (1 << 11); /* Force measurement on delay-lines */
394 mmdc0->mpmur0 = reg;
395 if (i->dsize > 1)
396 mmdc1->mpmur0 = reg;
397
398 /* Step 1: configuration request */
399 mmdc0->mdscr = (u32)(1 << 15); /* config request */
400
401 /* Step 2: Timing configuration */
402 reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |
403 (tfaw << 4) | tcl;
404 mmdc0->mdcfg0 = reg;
405 reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |
406 (1 << 15) | /* trpa */
407 (twr << 9) | (tmrd << 5) | tcwl;
408 mmdc0->mdcfg1 = reg;
409 reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
410 mmdc0->mdcfg2 = reg;
411 reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
412 (todtlon << 12) | (todt_idle_off << 4);
413 mmdc0->mdotc = reg;
414 mmdc0->mdasp = CS0_END; /* CS addressing */
415
416 /* Step 3: Configure DDR type */
417 reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |
418 (i->mif3_mode << 9) | (i->ralat << 6);
419 mmdc0->mdmisc = reg;
420
421 /* Step 4: Configure delay while leaving reset */
422 reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);
423 mmdc0->mdor = reg;
424
425 /* Step 5: Configure DDR physical parameters (density and burst len) */
Marek Vasut4a463602014-08-04 01:47:10 +0200[diff] [blame]426 coladdr = m->coladdr;
427 if (m->coladdr == 8) /* 8-bit COL is 0x3 */
428 coladdr += 4;
429 else if (m->coladdr == 12) /* 12-bit COL is 0x4 */
430 coladdr += 1;
Tim Harvey8ab871b2014-06-02 16:13:23 -0700[diff] [blame]431 reg = (m->rowaddr - 11) << 24 | /* ROW */
Marek Vasut4a463602014-08-04 01:47:10 +0200[diff] [blame]432 (coladdr - 9) << 20 | /* COL */
Tim Harvey8ab871b2014-06-02 16:13:23 -0700[diff] [blame]433 (1 << 19) | /* Burst Length = 8 for DDR3 */
434 (i->dsize << 16); /* DDR data bus size */
435 mmdc0->mdctl = reg;
436
437 /* Step 6: Perform ZQ calibration */
438 reg = (u32)0xa1390001; /* one-time HW ZQ calib */
439 mmdc0->mpzqhwctrl = reg;
440 if (i->dsize > 1)
441 mmdc1->mpzqhwctrl = reg;
442
443 /* Step 7: Enable MMDC with desired chip select */
444 reg = mmdc0->mdctl |
445 (1 << 31) | /* SDE_0 for CS0 */
446 ((i->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
447 mmdc0->mdctl = reg;
448
449 /* Step 8: Write Mode Registers to Init DDR3 devices */
450 for (cs = 0; cs < i->ncs; cs++) {
451 /* MR2 */
452 reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
453 ((tcwl - 3) & 3) << 3;
454 mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
455 /* MR3 */
456 mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
457 /* MR1 */
458 reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |
459 ((i->rtt_nom & 2) ? 1 : 0) << 6;
460 mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);
461 reg = ((tcl - 1) << 4) | /* CAS */
462 (1 << 8) | /* DLL Reset */
463 ((twr - 3) << 9); /* Write Recovery */
464 /* MR0 */
465 mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
466 /* ZQ calibration */
467 reg = (1 << 10);
468 mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
469 }
470
471 /* Step 10: Power down control and self-refresh */
472 reg = (tcke & 0x7) << 16 |
473 5 << 12 | /* PWDT_1: 256 cycles */
474 5 << 8 | /* PWDT_0: 256 cycles */
475 1 << 6 | /* BOTH_CS_PD */
476 (tcksrx & 0x7) << 3 |
477 (tcksre & 0x7);
478 mmdc0->mdpdc = reg;
479 mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
480
481 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
482 mmdc0->mpzqhwctrl = (u32)0xa1390003;
483 if (i->dsize > 1)
484 mmdc1->mpzqhwctrl = (u32)0xa1390003;
485
486 /* Step 12: Configure and activate periodic refresh */
487 reg = (1 << 14) | /* REF_SEL: Periodic refresh cycles of 32kHz */
488 (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
489 mmdc0->mdref = reg;
490
491 /* Step 13: Deassert config request - init complete */
492 mmdc0->mdscr = (u32)0x00000000;
493
494 /* wait for auto-ZQ calibration to complete */
495 mdelay(1);
496}