Blame - arch/arc/Kconfig - filogic/uboot

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Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	1	menu "ARC architecture"
				2	depends on ARC
				3
				4	config SYS_ARCH
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	5	default "arc"
				6
Alexey Brodkin	7739f9f	2014-12-25 18:47:45 +0300	[diff] [blame]	7	config SYS_CPU
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	8	default "arcv1" if ISA_ARCOMPACT
				9	default "arcv2" if ISA_ARCV2
Alexey Brodkin	7739f9f	2014-12-25 18:47:45 +0300	[diff] [blame]	10
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	11	choice
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	12	prompt "ARC Instruction Set"
				13	default ISA_ARCOMPACT
				14
				15	config ISA_ARCOMPACT
				16	bool "ARCompact ISA"
				17	help
				18	The original ARC ISA of ARC600/700 cores
				19
				20	config ISA_ARCV2
				21	bool "ARC ISA v2"
				22	help
				23	ISA for the Next Generation ARC-HS cores
				24
				25	endchoice
				26
				27	choice
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	28	prompt "CPU selection"
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	29	default CPU_ARC770D if ISA_ARCOMPACT
				30	default CPU_ARCHS38 if ISA_ARCV2
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	31
				32	config CPU_ARC750D
				33	bool "ARC 750D"
				34	select ARC_MMU_V2
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	35	depends on ISA_ARCOMPACT
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	36	help
				37	Choose this option to build an U-Boot for ARC750D CPU.
				38
				39	config CPU_ARC770D
				40	bool "ARC 770D"
				41	select ARC_MMU_V3
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	42	depends on ISA_ARCOMPACT
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	43	help
				44	Choose this option to build an U-Boot for ARC770D CPU.
				45
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	46	config CPU_ARCEM6
				47	bool "ARC EM6"
				48	select ARC_MMU_ABSENT
				49	depends on ISA_ARCV2
				50	help
				51	Next Generation ARC Core based on ISA-v2 ISA without MMU.
				52
				53	config CPU_ARCHS36
				54	bool "ARC HS36"
				55	select ARC_MMU_ABSENT
				56	depends on ISA_ARCV2
				57	help
				58	Next Generation ARC Core based on ISA-v2 ISA without MMU.
				59
				60	config CPU_ARCHS38
				61	bool "ARC HS38"
				62	select ARC_MMU_V4
				63	depends on ISA_ARCV2
				64	help
				65	Next Generation ARC Core based on ISA-v2 ISA with MMU.
				66
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	67	endchoice
				68
				69	choice
				70	prompt "MMU Version"
				71	default ARC_MMU_V3 if CPU_ARC770D
				72	default ARC_MMU_V2 if CPU_ARC750D
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	73	default ARC_MMU_ABSENT if CPU_ARCEM6
				74	default ARC_MMU_ABSENT if CPU_ARCHS36
				75	default ARC_MMU_V4 if CPU_ARCHS38
				76
				77	config ARC_MMU_ABSENT
				78	bool "No MMU"
				79	help
				80	No MMU
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	81
				82	config ARC_MMU_V2
				83	bool "MMU v2"
				84	depends on CPU_ARC750D
				85	help
				86	Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
				87	when 2 D-TLB and 1 I-TLB entries index into same 2way set.
				88
				89	config ARC_MMU_V3
				90	bool "MMU v3"
				91	depends on CPU_ARC770D
				92	help
				93	Introduced with ARC700 4.10: New Features
				94	Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
				95	Shared Address Spaces (SASID)
				96
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	97	config ARC_MMU_V4
				98	bool "MMU v4"
				99	depends on CPU_ARCHS38
				100	help
				101	Introduced as a part of ARC HS38 release.
				102
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	103	endchoice
				104
Alexey Brodkin	cbd76c3	2015-02-03 13:58:14 +0300	[diff] [blame]	105	config CPU_BIG_ENDIAN
				106	bool "Enable Big Endian Mode"
				107	default n
				108	help
				109	Build kernel for Big Endian Mode of ARC CPU
				110
Alexey Brodkin	6b95cca	2015-02-03 13:58:13 +0300	[diff] [blame]	111	config SYS_ICACHE_OFF
				112	bool "Do not use Instruction Cache"
				113	default n
				114
				115	config SYS_DCACHE_OFF
				116	bool "Do not use Data Cache"
				117	default n
				118
				119	config ARC_CACHE_LINE_SHIFT
				120	int "Cache Line Length (as power of 2)"
				121	range 5 7
				122	default "6"
Alexey Brodkin	bc9f197	2015-03-17 14:26:43 +0300	[diff] [blame]	123	depends on !SYS_DCACHE_OFF \|\| !SYS_ICACHE_OFF
Alexey Brodkin	6b95cca	2015-02-03 13:58:13 +0300	[diff] [blame]	124	help
				125	Starting with ARC700 4.9, Cache line length is configurable,
				126	This option specifies "N", with Line-len = 2 power N
				127	So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
				128	Linux only supports same line lengths for I and D caches.
				129
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	130	choice
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	131	prompt "Target select"
Joe Hershberger	f069960	2015-05-12 14:46:23 -0500	[diff] [blame]	132	optional
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	133
				134	config TARGET_TB100
				135	bool "Support tb100"
				136
				137	config TARGET_ARCANGEL4
				138	bool "Support arcangel4"
				139
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	140	config TARGET_AXS101
				141	bool "Support axs101"
				142
				143	endchoice
				144
				145	source "board/abilis/tb100/Kconfig"
				146	source "board/synopsys/Kconfig"
				147	source "board/synopsys/axs101/Kconfig"
				148
				149	endmenu