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Stefano Babice1b6f592010-07-06 19:32:09 +02001/*
2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
5 *
6 * Configuration settings for the MX51-3Stack Freescale board.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
Stefano Babice1b6f592010-07-06 19:32:09 +020027
28#define CONFIG_MX51 /* in a mx51 */
Fabio Estevam6b524c42011-05-10 08:13:56 +000029#define CONFIG_SYS_TEXT_BASE 0x97800000
Stefano Babice1b6f592010-07-06 19:32:09 +020030
Liu Hui-R64343baa2d782011-01-03 22:27:35 +000031#include <asm/arch/imx-regs.h>
32
Jason Liue7a7ed22010-10-18 11:09:26 +080033#define CONFIG_SYS_MX5_HCLK 24000000
34#define CONFIG_SYS_MX5_CLK32 32768
Stefano Babice1b6f592010-07-06 19:32:09 +020035#define CONFIG_DISPLAY_CPUINFO
36#define CONFIG_DISPLAY_BOARDINFO
37
38#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
Stefano Babice1b6f592010-07-06 19:32:09 +020039#define CONFIG_SETUP_MEMORY_TAGS
40#define CONFIG_INITRD_TAG
Helmut Raigerd5a184b2011-10-20 04:19:47 +000041#define CONFIG_BOARD_LATE_INIT
Stefano Babice1b6f592010-07-06 19:32:09 +020042
Stefano Babic0da928a2011-10-27 14:30:27 +020043#ifndef MACH_TYPE_TTC_VISION2
44#define MACH_TYPE_TTC_VISION2 2775
45#endif
Fabio Estevam9f55dc02011-09-23 02:50:51 +000046#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
47
Stefano Babice1b6f592010-07-06 19:32:09 +020048/*
49 * Size of malloc() pool
50 */
Stefano Babic61852442011-09-28 11:21:15 +020051#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Stefano Babice1b6f592010-07-06 19:32:09 +020052
Stefano Babice1b6f592010-07-06 19:32:09 +020053/*
54 * Hardware drivers
55 */
56#define CONFIG_MXC_UART
Stefano Babic1ca47d92011-11-22 15:22:39 +010057#define CONFIG_MXC_UART_BASE UART3_BASE
Stefano Babice1b6f592010-07-06 19:32:09 +020058#define CONFIG_MXC_GPIO
59#define CONFIG_MXC_SPI
60#define CONFIG_HW_WATCHDOG
61
62 /*
63 * SPI Configs
64 * */
65#define CONFIG_FSL_SF
66#define CONFIG_CMD_SF
67
68#define CONFIG_SPI_FLASH
69#define CONFIG_SPI_FLASH_STMICRO
70
71/*
72 * Use gpio 4 pin 25 as chip select for SPI flash
73 * This corresponds to gpio 121
74 */
Fabio Estevam608e9092012-03-22 14:29:04 +000075#define CONFIG_SF_DEFAULT_CS (1 | (121 << 8))
Stefano Babice1b6f592010-07-06 19:32:09 +020076#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
77#define CONFIG_SF_DEFAULT_SPEED 25000000
78
79#define CONFIG_ENV_SPI_CS (1 | (121 << 8))
80#define CONFIG_ENV_SPI_BUS 0
81#define CONFIG_ENV_SPI_MAX_HZ 25000000
82#define CONFIG_ENV_SPI_MODE SPI_MODE_0
83
84#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
85#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
86#define CONFIG_ENV_SIZE (4 * 1024)
87
88#define CONFIG_FSL_ENV_IN_SF
89#define CONFIG_ENV_IS_IN_SPI_FLASH
90
91/* PMIC Controller */
Stefano Babic470760e2011-10-02 12:58:03 +020092#define CONFIG_PMIC
93#define CONFIG_PMIC_SPI
94#define CONFIG_PMIC_FSL
Stefano Babice1b6f592010-07-06 19:32:09 +020095#define CONFIG_FSL_PMIC_BUS 0
96#define CONFIG_FSL_PMIC_CS 0
97#define CONFIG_FSL_PMIC_CLK 2500000
98#define CONFIG_FSL_PMIC_MODE SPI_MODE_0
Stefano Babic470760e2011-10-02 12:58:03 +020099#define CONFIG_FSL_PMIC_BITLEN 32
Fabio Estevam3f8d1782011-10-24 06:44:15 +0000100#define CONFIG_RTC_MC13XXX
Stefano Babice1b6f592010-07-06 19:32:09 +0200101
102/*
103 * MMC Configs
104 */
105#define CONFIG_FSL_ESDHC
106#ifdef CONFIG_FSL_ESDHC
107#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000)
108#define CONFIG_SYS_FSL_ESDHC_NUM 1
109
110#define CONFIG_MMC
111
112#define CONFIG_CMD_MMC
113#define CONFIG_GENERIC_MMC
114#define CONFIG_CMD_FAT
115#define CONFIG_DOS_PARTITION
116#endif
117
118#define CONFIG_CMD_DATE
119
120/*
121 * Eth Configs
122 */
123#define CONFIG_HAS_ETH1
Stefano Babice1b6f592010-07-06 19:32:09 +0200124#define CONFIG_MII
Stefano Babice1b6f592010-07-06 19:32:09 +0200125
126#define CONFIG_FEC_MXC
127#define IMX_FEC_BASE FEC_BASE_ADDR
128#define CONFIG_FEC_MXC_PHYADDR 0x1F
129
130#define CONFIG_CMD_PING
131#define CONFIG_CMD_MII
132#define CONFIG_CMD_NET
133
134/* allow to overwrite serial and ethaddr */
135#define CONFIG_ENV_OVERWRITE
136#define CONFIG_CONS_INDEX 3
137#define CONFIG_BAUDRATE 115200
Stefano Babice1b6f592010-07-06 19:32:09 +0200138
139/***********************************************************
140 * Command definition
141 ***********************************************************/
142
143#include <config_cmd_default.h>
144
145#define CONFIG_CMD_SPI
146#undef CONFIG_CMD_IMLS
147
148#define CONFIG_BOOTDELAY 3
149
150#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
151
152#define CONFIG_EXTRA_ENV_SETTINGS \
153 "netdev=eth0\0" \
154 "loadaddr=0x90800000\0"
155
156/*
157 * Miscellaneous configurable options
158 */
159#define CONFIG_SYS_LONGHELP
160#define CONFIG_SYS_PROMPT "Vision II U-boot > "
161#define CONFIG_AUTO_COMPLETE
162#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
163
164/* Print Buffer Size */
165#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
166 sizeof(CONFIG_SYS_PROMPT) + 16)
167#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
168#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
169
170#define CONFIG_SYS_MEMTEST_START 0x90000000
171#define CONFIG_SYS_MEMTEST_END 0x10000
172
173#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
174
175#define CONFIG_SYS_HZ 1000
176#define CONFIG_CMDLINE_EDITING
177#define CONFIG_SYS_HUSH_PARSER
Stefano Babice1b6f592010-07-06 19:32:09 +0200178
179/*
180 * Stack sizes
181 */
182#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
183
184/*
185 * Physical Memory Map
186 */
187#define CONFIG_NR_DRAM_BANKS 2
188#define PHYS_SDRAM_1 CSD0_BASE_ADDR
189#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
190#define PHYS_SDRAM_2 CSD1_BASE_ADDR
191#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024)
Stefano Babic23f01dc2011-01-21 17:39:03 +0100192#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
193#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
194#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
195
196#define CONFIG_SYS_INIT_SP_OFFSET \
197 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
198#define CONFIG_SYS_INIT_SP_ADDR \
199 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
Stefano Babice1b6f592010-07-06 19:32:09 +0200200
Stefano Babice1b6f592010-07-06 19:32:09 +0200201#define CONFIG_BOARD_EARLY_INIT_F
202
203/* 166 MHz DDR RAM */
204#define CONFIG_SYS_DDR_CLKSEL 0
205#define CONFIG_SYS_CLKTL_CBCDR 0x19239100
206
207#define CONFIG_SYS_NO_FLASH
208
Stefano Babic445a4822010-10-21 10:34:39 +0200209/*
210 * Framebuffer and LCD
211 */
212#define CONFIG_PREBOOT
Stefano Babic61852442011-09-28 11:21:15 +0200213#define CONFIG_VIDEO
Fabio Estevamc6dd2e02012-05-31 07:23:56 +0000214#define CONFIG_VIDEO_IPUV3
Stefano Babic61852442011-09-28 11:21:15 +0200215#define CONFIG_CFB_CONSOLE
216#define CONFIG_VGA_AS_SINGLE_DEVICE
217#define CONFIG_VIDEO_BMP_RLE8
Stefano Babic445a4822010-10-21 10:34:39 +0200218#define CONFIG_SPLASH_SCREEN
219#define CONFIG_CMD_BMP
220#define CONFIG_BMP_16BPP
Fabio Estevam82692e22012-05-31 07:24:00 +0000221#define CONFIG_IPUV3_CLK 133000000
Stefano Babic445a4822010-10-21 10:34:39 +0200222
Stefano Babice1b6f592010-07-06 19:32:09 +0200223#endif /* __CONFIG_H */