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git01.mediatek.com / filogic / uboot / b27877510da9536a35cb6c115f450188bb7ecaf6 / . / board / siemens / common / Kconfig
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Tom Rini29e05952022-06-10 22:59:35 -0400[diff] [blame]1config FACTORYSET
2 bool
Enrico Letod46260e2024-11-23 17:53:03 +0100[diff] [blame]3
4config DDR_SI_TEST
5 bool "DDR signal integrity test implementations"
6 default y