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git01.mediatek.com / filogic / uboot / 591da92aa59ba7c07d5e6271597ae19cc373a118 / . / drivers / pinctrl / nuvoton / pinctrl-npcm7xx.c
blob: f6e20415e2eabd8c4ad18d515638db73d2e3222a [file] [log] [blame]
Jim Liud949c122022-05-17 16:30:32 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2020 Nuvoton Technology Corp.
4 * Author: Joseph Liu <kwliu@nuvoton.com>
5 * Author: Tomer Maimon <tomer.maimon@nuvoton.com>
6 */
7
8#include <dm.h>
9#include <errno.h>
10#include <regmap.h>
11#include <syscon.h>
12#include <asm/io.h>
13#include <dm/device_compat.h>
14#include <dm/pinctrl.h>
15
16/* GCR registers */
17#define NPCM7XX_GCR_PDID 0x00
18#define NPCM7XX_GCR_MFSEL1 0x0C
19#define NPCM7XX_GCR_MFSEL2 0x10
20#define NPCM7XX_GCR_MFSEL3 0x64
21#define NPCM7XX_GCR_MFSEL4 0xb0
22#define NPCM7XX_GCR_CPCTL 0xD0
23#define NPCM7XX_GCR_CP2BST 0xD4
24#define NPCM7XX_GCR_B2CPNT 0xD8
25#define NPCM7XX_GCR_I2CSEGSEL 0xE0
26#define NPCM7XX_GCR_I2CSEGCTL 0xE4
27#define NPCM7XX_GCR_INTCR2 0x60
28#define NPCM7XX_GCR_SRCNT 0x68
29#define NPCM7XX_GCR_RESSR 0x6C
30#define NPCM7XX_GCR_FLOCKR1 0x74
31#define NPCM7XX_GCR_DSCNT 0x78
32
33#define SRCNT_ESPI BIT(3)
34
35/* reset registers */
36#define NPCM7XX_RST_WD0RCR 0x38
37#define NPCM7XX_RST_WD1RCR 0x3C
38#define NPCM7XX_RST_WD2RCR 0x40
39#define NPCM7XX_RST_SWRSTC1 0x44
40#define NPCM7XX_RST_SWRSTC2 0x48
41#define NPCM7XX_RST_SWRSTC3 0x4C
42#define NPCM7XX_RST_SWRSTC4 0x50
43#define NPCM7XX_RST_CORSTC 0x5C
44
45#define PORST BIT(31)
46#define CORST BIT(30)
47#define WD0RST BIT(29)
48#define WD1RST BIT(24)
49#define WD2RST BIT(23)
50
51#define GPIOX_MODULE_RESET 16
52#define CA9C_RESET BIT(0)
53
54/* GPIO registers */
55#define NPCM7XX_GP_N_TLOCK1 0x00
56#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */
57#define NPCM7XX_GP_N_POL 0x08 /* Polarity */
58#define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */
59#define NPCM7XX_GP_N_OE 0x10 /* Output Enable */
60#define NPCM7XX_GP_N_OTYP 0x14
61#define NPCM7XX_GP_N_MP 0x18
62#define NPCM7XX_GP_N_PU 0x1c /* Pull-up */
63#define NPCM7XX_GP_N_PD 0x20 /* Pull-down */
64#define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */
65#define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */
66#define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */
67#define NPCM7XX_GP_N_OBL0 0x30
68#define NPCM7XX_GP_N_OBL1 0x34
69#define NPCM7XX_GP_N_OBL2 0x38
70#define NPCM7XX_GP_N_OBL3 0x3c
71#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */
72#define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */
73#define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */
74#define NPCM7XX_GP_N_EVST 0x4c /* Event Status */
75#define NPCM7XX_GP_N_SPLCK 0x50
76#define NPCM7XX_GP_N_MPLCK 0x54
77#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */
78#define NPCM7XX_GP_N_OSRC 0x5c
79#define NPCM7XX_GP_N_ODSC 0x60
80#define NPCM7XX_GP_N_DOS 0x68 /* Data OUT Set */
81#define NPCM7XX_GP_N_DOC 0x6c /* Data OUT Clear */
82#define NPCM7XX_GP_N_OES 0x70 /* Output Enable Set */
83#define NPCM7XX_GP_N_OEC 0x74 /* Output Enable Clear */
84#define NPCM7XX_GP_N_TLOCK2 0x7c
85
86#define NPCM7XX_GPIO_BANK_OFFSET 0x1000
87#define NPCM7XX_GPIO_PER_BITS 32
88#define NPCM7XX_GPIO_PER_BANK 32
89#define NPCM7XX_GPIO_BANK_NUM 8
90#define NPCM7XX_GCR_NONE 0
91
92/* pinmux handing in the pinctrl driver*/
93static const int smb0_pins[] = { 115, 114 };
94static const int smb0b_pins[] = { 195, 194 };
95static const int smb0c_pins[] = { 202, 196 };
96static const int smb0d_pins[] = { 198, 199 };
97static const int smb0den_pins[] = { 197 };
98
99static const int smb1_pins[] = { 117, 116 };
100static const int smb1b_pins[] = { 126, 127 };
101static const int smb1c_pins[] = { 124, 125 };
102static const int smb1d_pins[] = { 4, 5 };
103
104static const int smb2_pins[] = { 119, 118 };
105static const int smb2b_pins[] = { 122, 123 };
106static const int smb2c_pins[] = { 120, 121 };
107static const int smb2d_pins[] = { 6, 7 };
108
109static const int smb3_pins[] = { 30, 31 };
110static const int smb3b_pins[] = { 39, 40 };
111static const int smb3c_pins[] = { 37, 38 };
112static const int smb3d_pins[] = { 59, 60 };
113
114static const int smb4_pins[] = { 28, 29 };
115static const int smb4b_pins[] = { 18, 19 };
116static const int smb4c_pins[] = { 20, 21 };
117static const int smb4d_pins[] = { 22, 23 };
118static const int smb4den_pins[] = { 17 };
119
120static const int smb5_pins[] = { 26, 27 };
121static const int smb5b_pins[] = { 13, 12 };
122static const int smb5c_pins[] = { 15, 14 };
123static const int smb5d_pins[] = { 94, 93 };
124static const int ga20kbc_pins[] = { 94, 93 };
125
126static const int smb6_pins[] = { 172, 171 };
127static const int smb7_pins[] = { 174, 173 };
128static const int smb8_pins[] = { 129, 128 };
129static const int smb9_pins[] = { 131, 130 };
130static const int smb10_pins[] = { 133, 132 };
131static const int smb11_pins[] = { 135, 134 };
132static const int smb12_pins[] = { 221, 220 };
133static const int smb13_pins[] = { 223, 222 };
134static const int smb14_pins[] = { 22, 23 };
135static const int smb15_pins[] = { 20, 21 };
136
137static const int fanin0_pins[] = { 64 };
138static const int fanin1_pins[] = { 65 };
139static const int fanin2_pins[] = { 66 };
140static const int fanin3_pins[] = { 67 };
141static const int fanin4_pins[] = { 68 };
142static const int fanin5_pins[] = { 69 };
143static const int fanin6_pins[] = { 70 };
144static const int fanin7_pins[] = { 71 };
145static const int fanin8_pins[] = { 72 };
146static const int fanin9_pins[] = { 73 };
147static const int fanin10_pins[] = { 74 };
148static const int fanin11_pins[] = { 75 };
149static const int fanin12_pins[] = { 76 };
150static const int fanin13_pins[] = { 77 };
151static const int fanin14_pins[] = { 78 };
152static const int fanin15_pins[] = { 79 };
153static const int faninx_pins[] = { 175, 176, 177, 203 };
154
155static const int pwm0_pins[] = { 80 };
156static const int pwm1_pins[] = { 81 };
157static const int pwm2_pins[] = { 82 };
158static const int pwm3_pins[] = { 83 };
159static const int pwm4_pins[] = { 144 };
160static const int pwm5_pins[] = { 145 };
161static const int pwm6_pins[] = { 146 };
162static const int pwm7_pins[] = { 147 };
163
164static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
165static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
166
167/* RGMII 1 pin group */
168static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105,
169 106, 107 };
170/* RGMII 1 MD interface pin group */
171static const int rg1mdio_pins[] = { 108, 109 };
172
173/* RGMII 2 pin group */
174static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
175 213, 214, 215 };
176/* RGMII 2 MD interface pin group */
177static const int rg2mdio_pins[] = { 216, 217 };
178
179static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
180 213, 214, 215, 216, 217 };
181/* Serial I/O Expander 1 */
182static const int iox1_pins[] = { 0, 1, 2, 3 };
183/* Serial I/O Expander 2 */
184static const int iox2_pins[] = { 4, 5, 6, 7 };
185/* Host Serial I/O Expander 2 */
186static const int ioxh_pins[] = { 10, 11, 24, 25 };
187
188static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
189static const int mmcwp_pins[] = { 153 };
190static const int mmccd_pins[] = { 155 };
191static const int mmcrst_pins[] = { 155 };
192static const int mmc8_pins[] = { 148, 149, 150, 151 };
193
194/* RMII 1 pin groups */
195static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
196static const int r1err_pins[] = { 56 };
197static const int r1md_pins[] = { 57, 58 };
198
199/* RMII 2 pin groups */
200static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
201static const int r2err_pins[] = { 90 };
202static const int r2md_pins[] = { 91, 92 };
203
204static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
205static const int sd1pwr_pins[] = { 143 };
206
207static const int wdog1_pins[] = { 218 };
208static const int wdog2_pins[] = { 219 };
209
210/* BMC serial port 0 */
211static const int bmcuart0a_pins[] = { 41, 42 };
212static const int bmcuart0b_pins[] = { 48, 49 };
213
214static const int bmcuart1_pins[] = { 43, 44, 62, 63 };
215
216/* System Control Interrupt and Power Management Event pin group */
217static const int scipme_pins[] = { 169 };
218/* System Management Interrupt pin group */
219static const int sci_pins[] = { 170 };
220/* Serial Interrupt Line pin group */
221static const int serirq_pins[] = { 162 };
222
223static const int clkout_pins[] = { 160 };
224static const int clkreq_pins[] = { 231 };
225
226static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };
227/* Graphics SPI Clock pin group */
228static const int gspi_pins[] = { 12, 13, 14, 15 };
229
230static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
231static const int spixcs1_pins[] = { 228 };
232
233static const int pspi1_pins[] = { 175, 176, 177 };
234static const int pspi2_pins[] = { 17, 18, 19 };
235
236static const int spi0cs1_pins[] = { 32 };
237
238static const int spi3_pins[] = { 183, 184, 185, 186 };
239static const int spi3cs1_pins[] = { 187 };
240static const int spi3quad_pins[] = { 188, 189 };
241static const int spi3cs2_pins[] = { 188 };
242static const int spi3cs3_pins[] = { 189 };
243
244static const int ddc_pins[] = { 204, 205, 206, 207 };
245
246static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
247static const int lpcclk_pins[] = { 168 };
248static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
249
250static const int lkgpo0_pins[] = { 16 };
251static const int lkgpo1_pins[] = { 8 };
252static const int lkgpo2_pins[] = { 9 };
253
254static const int nprd_smi_pins[] = { 190 };
255
256static const int hgpio0_pins[] = { 20 };
257static const int hgpio1_pins[] = { 21 };
258static const int hgpio2_pins[] = { 22 };
259static const int hgpio3_pins[] = { 23 };
260static const int hgpio4_pins[] = { 24 };
261static const int hgpio5_pins[] = { 25 };
262static const int hgpio6_pins[] = { 59 };
263static const int hgpio7_pins[] = { 60 };
264
265/*
266 * pin: name, number
267 * group: name, npins, pins
268 * function: name, ngroups, groups
269 */
270struct npcm7xx_group {
271 const char *name;
272 const int *pins;
273 int npins;
274};
275
276#define NPCM7XX_GRPS \
277 NPCM7XX_GRP(smb0), \
278 NPCM7XX_GRP(smb0b), \
279 NPCM7XX_GRP(smb0c), \
280 NPCM7XX_GRP(smb0d), \
281 NPCM7XX_GRP(smb0den), \
282 NPCM7XX_GRP(smb1), \
283 NPCM7XX_GRP(smb1b), \
284 NPCM7XX_GRP(smb1c), \
285 NPCM7XX_GRP(smb1d), \
286 NPCM7XX_GRP(smb2), \
287 NPCM7XX_GRP(smb2b), \
288 NPCM7XX_GRP(smb2c), \
289 NPCM7XX_GRP(smb2d), \
290 NPCM7XX_GRP(smb3), \
291 NPCM7XX_GRP(smb3b), \
292 NPCM7XX_GRP(smb3c), \
293 NPCM7XX_GRP(smb3d), \
294 NPCM7XX_GRP(smb4), \
295 NPCM7XX_GRP(smb4b), \
296 NPCM7XX_GRP(smb4c), \
297 NPCM7XX_GRP(smb4d), \
298 NPCM7XX_GRP(smb4den), \
299 NPCM7XX_GRP(smb5), \
300 NPCM7XX_GRP(smb5b), \
301 NPCM7XX_GRP(smb5c), \
302 NPCM7XX_GRP(smb5d), \
303 NPCM7XX_GRP(ga20kbc), \
304 NPCM7XX_GRP(smb6), \
305 NPCM7XX_GRP(smb7), \
306 NPCM7XX_GRP(smb8), \
307 NPCM7XX_GRP(smb9), \
308 NPCM7XX_GRP(smb10), \
309 NPCM7XX_GRP(smb11), \
310 NPCM7XX_GRP(smb12), \
311 NPCM7XX_GRP(smb13), \
312 NPCM7XX_GRP(smb14), \
313 NPCM7XX_GRP(smb15), \
314 NPCM7XX_GRP(fanin0), \
315 NPCM7XX_GRP(fanin1), \
316 NPCM7XX_GRP(fanin2), \
317 NPCM7XX_GRP(fanin3), \
318 NPCM7XX_GRP(fanin4), \
319 NPCM7XX_GRP(fanin5), \
320 NPCM7XX_GRP(fanin6), \
321 NPCM7XX_GRP(fanin7), \
322 NPCM7XX_GRP(fanin8), \
323 NPCM7XX_GRP(fanin9), \
324 NPCM7XX_GRP(fanin10), \
325 NPCM7XX_GRP(fanin11), \
326 NPCM7XX_GRP(fanin12), \
327 NPCM7XX_GRP(fanin13), \
328 NPCM7XX_GRP(fanin14), \
329 NPCM7XX_GRP(fanin15), \
330 NPCM7XX_GRP(faninx), \
331 NPCM7XX_GRP(pwm0), \
332 NPCM7XX_GRP(pwm1), \
333 NPCM7XX_GRP(pwm2), \
334 NPCM7XX_GRP(pwm3), \
335 NPCM7XX_GRP(pwm4), \
336 NPCM7XX_GRP(pwm5), \
337 NPCM7XX_GRP(pwm6), \
338 NPCM7XX_GRP(pwm7), \
339 NPCM7XX_GRP(rg1), \
340 NPCM7XX_GRP(rg1mdio), \
341 NPCM7XX_GRP(rg2), \
342 NPCM7XX_GRP(rg2mdio), \
343 NPCM7XX_GRP(ddr), \
344 NPCM7XX_GRP(uart1), \
345 NPCM7XX_GRP(uart2), \
346 NPCM7XX_GRP(bmcuart0a), \
347 NPCM7XX_GRP(bmcuart0b), \
348 NPCM7XX_GRP(bmcuart1), \
349 NPCM7XX_GRP(iox1), \
350 NPCM7XX_GRP(iox2), \
351 NPCM7XX_GRP(ioxh), \
352 NPCM7XX_GRP(gspi), \
353 NPCM7XX_GRP(mmc), \
354 NPCM7XX_GRP(mmcwp), \
355 NPCM7XX_GRP(mmccd), \
356 NPCM7XX_GRP(mmcrst), \
357 NPCM7XX_GRP(mmc8), \
358 NPCM7XX_GRP(r1), \
359 NPCM7XX_GRP(r1err), \
360 NPCM7XX_GRP(r1md), \
361 NPCM7XX_GRP(r2), \
362 NPCM7XX_GRP(r2err), \
363 NPCM7XX_GRP(r2md), \
364 NPCM7XX_GRP(sd1), \
365 NPCM7XX_GRP(sd1pwr), \
366 NPCM7XX_GRP(wdog1), \
367 NPCM7XX_GRP(wdog2), \
368 NPCM7XX_GRP(scipme), \
369 NPCM7XX_GRP(sci), \
370 NPCM7XX_GRP(serirq), \
371 NPCM7XX_GRP(jtag2), \
372 NPCM7XX_GRP(spix), \
373 NPCM7XX_GRP(spixcs1), \
374 NPCM7XX_GRP(pspi1), \
375 NPCM7XX_GRP(pspi2), \
376 NPCM7XX_GRP(ddc), \
377 NPCM7XX_GRP(clkreq), \
378 NPCM7XX_GRP(clkout), \
379 NPCM7XX_GRP(spi3), \
380 NPCM7XX_GRP(spi3cs1), \
381 NPCM7XX_GRP(spi3quad), \
382 NPCM7XX_GRP(spi3cs2), \
383 NPCM7XX_GRP(spi3cs3), \
384 NPCM7XX_GRP(spi0cs1), \
385 NPCM7XX_GRP(lpc), \
386 NPCM7XX_GRP(lpcclk), \
387 NPCM7XX_GRP(espi), \
388 NPCM7XX_GRP(lkgpo0), \
389 NPCM7XX_GRP(lkgpo1), \
390 NPCM7XX_GRP(lkgpo2), \
391 NPCM7XX_GRP(nprd_smi), \
392 NPCM7XX_GRP(hgpio0), \
393 NPCM7XX_GRP(hgpio1), \
394 NPCM7XX_GRP(hgpio2), \
395 NPCM7XX_GRP(hgpio3), \
396 NPCM7XX_GRP(hgpio4), \
397 NPCM7XX_GRP(hgpio5), \
398 NPCM7XX_GRP(hgpio6), \
399 NPCM7XX_GRP(hgpio7), \
400 \
401
402enum {
403#define NPCM7XX_GRP(x) fn_ ## x
404 NPCM7XX_GRPS
405 /* add placeholder for none/gpio */
406 NPCM7XX_GRP(none),
407 NPCM7XX_GRP(gpio),
408#undef NPCM7XX_GRP
409};
410
411static struct npcm7xx_group npcm7xx_groups[] = {
412#define NPCM7XX_GRP(x) { .name = #x, .pins = x ## _pins, \
413 .npins = ARRAY_SIZE(x ## _pins) }
414 NPCM7XX_GRPS
415#undef NPCM7XX_GRP
416};
417
418#define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a)
419#define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
420#define NPCM7XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
421 .groups = nm ## _grp }
422struct npcm7xx_func {
423 const char *name;
424 const unsigned int ngroups;
425 const char *const *groups;
426};
427
428NPCM7XX_SFUNC(smb0);
429NPCM7XX_SFUNC(smb0b);
430NPCM7XX_SFUNC(smb0c);
431NPCM7XX_SFUNC(smb0d);
432NPCM7XX_SFUNC(smb0den);
433NPCM7XX_SFUNC(smb1);
434NPCM7XX_SFUNC(smb1b);
435NPCM7XX_SFUNC(smb1c);
436NPCM7XX_SFUNC(smb1d);
437NPCM7XX_SFUNC(smb2);
438NPCM7XX_SFUNC(smb2b);
439NPCM7XX_SFUNC(smb2c);
440NPCM7XX_SFUNC(smb2d);
441NPCM7XX_SFUNC(smb3);
442NPCM7XX_SFUNC(smb3b);
443NPCM7XX_SFUNC(smb3c);
444NPCM7XX_SFUNC(smb3d);
445NPCM7XX_SFUNC(smb4);
446NPCM7XX_SFUNC(smb4b);
447NPCM7XX_SFUNC(smb4c);
448NPCM7XX_SFUNC(smb4d);
449NPCM7XX_SFUNC(smb4den);
450NPCM7XX_SFUNC(smb5);
451NPCM7XX_SFUNC(smb5b);
452NPCM7XX_SFUNC(smb5c);
453NPCM7XX_SFUNC(smb5d);
454NPCM7XX_SFUNC(ga20kbc);
455NPCM7XX_SFUNC(smb6);
456NPCM7XX_SFUNC(smb7);
457NPCM7XX_SFUNC(smb8);
458NPCM7XX_SFUNC(smb9);
459NPCM7XX_SFUNC(smb10);
460NPCM7XX_SFUNC(smb11);
461NPCM7XX_SFUNC(smb12);
462NPCM7XX_SFUNC(smb13);
463NPCM7XX_SFUNC(smb14);
464NPCM7XX_SFUNC(smb15);
465NPCM7XX_SFUNC(fanin0);
466NPCM7XX_SFUNC(fanin1);
467NPCM7XX_SFUNC(fanin2);
468NPCM7XX_SFUNC(fanin3);
469NPCM7XX_SFUNC(fanin4);
470NPCM7XX_SFUNC(fanin5);
471NPCM7XX_SFUNC(fanin6);
472NPCM7XX_SFUNC(fanin7);
473NPCM7XX_SFUNC(fanin8);
474NPCM7XX_SFUNC(fanin9);
475NPCM7XX_SFUNC(fanin10);
476NPCM7XX_SFUNC(fanin11);
477NPCM7XX_SFUNC(fanin12);
478NPCM7XX_SFUNC(fanin13);
479NPCM7XX_SFUNC(fanin14);
480NPCM7XX_SFUNC(fanin15);
481NPCM7XX_SFUNC(faninx);
482NPCM7XX_SFUNC(pwm0);
483NPCM7XX_SFUNC(pwm1);
484NPCM7XX_SFUNC(pwm2);
485NPCM7XX_SFUNC(pwm3);
486NPCM7XX_SFUNC(pwm4);
487NPCM7XX_SFUNC(pwm5);
488NPCM7XX_SFUNC(pwm6);
489NPCM7XX_SFUNC(pwm7);
490NPCM7XX_SFUNC(rg1);
491NPCM7XX_SFUNC(rg1mdio);
492NPCM7XX_SFUNC(rg2);
493NPCM7XX_SFUNC(rg2mdio);
494NPCM7XX_SFUNC(ddr);
495NPCM7XX_SFUNC(uart1);
496NPCM7XX_SFUNC(uart2);
497NPCM7XX_SFUNC(bmcuart0a);
498NPCM7XX_SFUNC(bmcuart0b);
499NPCM7XX_SFUNC(bmcuart1);
500NPCM7XX_SFUNC(iox1);
501NPCM7XX_SFUNC(iox2);
502NPCM7XX_SFUNC(ioxh);
503NPCM7XX_SFUNC(gspi);
504NPCM7XX_SFUNC(mmc);
505NPCM7XX_SFUNC(mmcwp);
506NPCM7XX_SFUNC(mmccd);
507NPCM7XX_SFUNC(mmcrst);
508NPCM7XX_SFUNC(mmc8);
509NPCM7XX_SFUNC(r1);
510NPCM7XX_SFUNC(r1err);
511NPCM7XX_SFUNC(r1md);
512NPCM7XX_SFUNC(r2);
513NPCM7XX_SFUNC(r2err);
514NPCM7XX_SFUNC(r2md);
515NPCM7XX_SFUNC(sd1);
516NPCM7XX_SFUNC(sd1pwr);
517NPCM7XX_SFUNC(wdog1);
518NPCM7XX_SFUNC(wdog2);
519NPCM7XX_SFUNC(scipme);
520NPCM7XX_SFUNC(sci);
521NPCM7XX_SFUNC(serirq);
522NPCM7XX_SFUNC(jtag2);
523NPCM7XX_SFUNC(spix);
524NPCM7XX_SFUNC(spixcs1);
525NPCM7XX_SFUNC(pspi1);
526NPCM7XX_SFUNC(pspi2);
527NPCM7XX_SFUNC(ddc);
528NPCM7XX_SFUNC(clkreq);
529NPCM7XX_SFUNC(clkout);
530NPCM7XX_SFUNC(spi3);
531NPCM7XX_SFUNC(spi3cs1);
532NPCM7XX_SFUNC(spi3quad);
533NPCM7XX_SFUNC(spi3cs2);
534NPCM7XX_SFUNC(spi3cs3);
535NPCM7XX_SFUNC(spi0cs1);
536NPCM7XX_SFUNC(lpc);
537NPCM7XX_SFUNC(lpcclk);
538NPCM7XX_SFUNC(espi);
539NPCM7XX_SFUNC(lkgpo0);
540NPCM7XX_SFUNC(lkgpo1);
541NPCM7XX_SFUNC(lkgpo2);
542NPCM7XX_SFUNC(nprd_smi);
543NPCM7XX_SFUNC(hgpio0);
544NPCM7XX_SFUNC(hgpio1);
545NPCM7XX_SFUNC(hgpio2);
546NPCM7XX_SFUNC(hgpio3);
547NPCM7XX_SFUNC(hgpio4);
548NPCM7XX_SFUNC(hgpio5);
549NPCM7XX_SFUNC(hgpio6);
550NPCM7XX_SFUNC(hgpio7);
551
552/* Function names */
553static struct npcm7xx_func npcm7xx_funcs[] = {
554 NPCM7XX_MKFUNC(smb0),
555 NPCM7XX_MKFUNC(smb0b),
556 NPCM7XX_MKFUNC(smb0c),
557 NPCM7XX_MKFUNC(smb0d),
558 NPCM7XX_MKFUNC(smb0den),
559 NPCM7XX_MKFUNC(smb1),
560 NPCM7XX_MKFUNC(smb1b),
561 NPCM7XX_MKFUNC(smb1c),
562 NPCM7XX_MKFUNC(smb1d),
563 NPCM7XX_MKFUNC(smb2),
564 NPCM7XX_MKFUNC(smb2b),
565 NPCM7XX_MKFUNC(smb2c),
566 NPCM7XX_MKFUNC(smb2d),
567 NPCM7XX_MKFUNC(smb3),
568 NPCM7XX_MKFUNC(smb3b),
569 NPCM7XX_MKFUNC(smb3c),
570 NPCM7XX_MKFUNC(smb3d),
571 NPCM7XX_MKFUNC(smb4),
572 NPCM7XX_MKFUNC(smb4b),
573 NPCM7XX_MKFUNC(smb4c),
574 NPCM7XX_MKFUNC(smb4d),
575 NPCM7XX_MKFUNC(smb4den),
576 NPCM7XX_MKFUNC(smb5),
577 NPCM7XX_MKFUNC(smb5b),
578 NPCM7XX_MKFUNC(smb5c),
579 NPCM7XX_MKFUNC(smb5d),
580 NPCM7XX_MKFUNC(ga20kbc),
581 NPCM7XX_MKFUNC(smb6),
582 NPCM7XX_MKFUNC(smb7),
583 NPCM7XX_MKFUNC(smb8),
584 NPCM7XX_MKFUNC(smb9),
585 NPCM7XX_MKFUNC(smb10),
586 NPCM7XX_MKFUNC(smb11),
587 NPCM7XX_MKFUNC(smb12),
588 NPCM7XX_MKFUNC(smb13),
589 NPCM7XX_MKFUNC(smb14),
590 NPCM7XX_MKFUNC(smb15),
591 NPCM7XX_MKFUNC(fanin0),
592 NPCM7XX_MKFUNC(fanin1),
593 NPCM7XX_MKFUNC(fanin2),
594 NPCM7XX_MKFUNC(fanin3),
595 NPCM7XX_MKFUNC(fanin4),
596 NPCM7XX_MKFUNC(fanin5),
597 NPCM7XX_MKFUNC(fanin6),
598 NPCM7XX_MKFUNC(fanin7),
599 NPCM7XX_MKFUNC(fanin8),
600 NPCM7XX_MKFUNC(fanin9),
601 NPCM7XX_MKFUNC(fanin10),
602 NPCM7XX_MKFUNC(fanin11),
603 NPCM7XX_MKFUNC(fanin12),
604 NPCM7XX_MKFUNC(fanin13),
605 NPCM7XX_MKFUNC(fanin14),
606 NPCM7XX_MKFUNC(fanin15),
607 NPCM7XX_MKFUNC(faninx),
608 NPCM7XX_MKFUNC(pwm0),
609 NPCM7XX_MKFUNC(pwm1),
610 NPCM7XX_MKFUNC(pwm2),
611 NPCM7XX_MKFUNC(pwm3),
612 NPCM7XX_MKFUNC(pwm4),
613 NPCM7XX_MKFUNC(pwm5),
614 NPCM7XX_MKFUNC(pwm6),
615 NPCM7XX_MKFUNC(pwm7),
616 NPCM7XX_MKFUNC(rg1),
617 NPCM7XX_MKFUNC(rg1mdio),
618 NPCM7XX_MKFUNC(rg2),
619 NPCM7XX_MKFUNC(rg2mdio),
620 NPCM7XX_MKFUNC(ddr),
621 NPCM7XX_MKFUNC(uart1),
622 NPCM7XX_MKFUNC(uart2),
623 NPCM7XX_MKFUNC(bmcuart0a),
624 NPCM7XX_MKFUNC(bmcuart0b),
625 NPCM7XX_MKFUNC(bmcuart1),
626 NPCM7XX_MKFUNC(iox1),
627 NPCM7XX_MKFUNC(iox2),
628 NPCM7XX_MKFUNC(ioxh),
629 NPCM7XX_MKFUNC(gspi),
630 NPCM7XX_MKFUNC(mmc),
631 NPCM7XX_MKFUNC(mmcwp),
632 NPCM7XX_MKFUNC(mmccd),
633 NPCM7XX_MKFUNC(mmcrst),
634 NPCM7XX_MKFUNC(mmc8),
635 NPCM7XX_MKFUNC(r1),
636 NPCM7XX_MKFUNC(r1err),
637 NPCM7XX_MKFUNC(r1md),
638 NPCM7XX_MKFUNC(r2),
639 NPCM7XX_MKFUNC(r2err),
640 NPCM7XX_MKFUNC(r2md),
641 NPCM7XX_MKFUNC(sd1),
642 NPCM7XX_MKFUNC(sd1pwr),
643 NPCM7XX_MKFUNC(wdog1),
644 NPCM7XX_MKFUNC(wdog2),
645 NPCM7XX_MKFUNC(scipme),
646 NPCM7XX_MKFUNC(sci),
647 NPCM7XX_MKFUNC(serirq),
648 NPCM7XX_MKFUNC(jtag2),
649 NPCM7XX_MKFUNC(spix),
650 NPCM7XX_MKFUNC(spixcs1),
651 NPCM7XX_MKFUNC(pspi1),
652 NPCM7XX_MKFUNC(pspi2),
653 NPCM7XX_MKFUNC(ddc),
654 NPCM7XX_MKFUNC(clkreq),
655 NPCM7XX_MKFUNC(clkout),
656 NPCM7XX_MKFUNC(spi3),
657 NPCM7XX_MKFUNC(spi3cs1),
658 NPCM7XX_MKFUNC(spi3quad),
659 NPCM7XX_MKFUNC(spi3cs2),
660 NPCM7XX_MKFUNC(spi3cs3),
661 NPCM7XX_MKFUNC(spi0cs1),
662 NPCM7XX_MKFUNC(lpc),
663 NPCM7XX_MKFUNC(lpcclk),
664 NPCM7XX_MKFUNC(espi),
665 NPCM7XX_MKFUNC(lkgpo0),
666 NPCM7XX_MKFUNC(lkgpo1),
667 NPCM7XX_MKFUNC(lkgpo2),
668 NPCM7XX_MKFUNC(nprd_smi),
669 NPCM7XX_MKFUNC(hgpio0),
670 NPCM7XX_MKFUNC(hgpio1),
671 NPCM7XX_MKFUNC(hgpio2),
672 NPCM7XX_MKFUNC(hgpio3),
673 NPCM7XX_MKFUNC(hgpio4),
674 NPCM7XX_MKFUNC(hgpio5),
675 NPCM7XX_MKFUNC(hgpio6),
676 NPCM7XX_MKFUNC(hgpio7),
677};
678
679#define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \
680 [a] { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \
681 .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \
682 .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \
683 .flag = k }
684
685/* Drive strength controlled by NPCM7XX_GP_N_ODSC */
686#define DRIVE_STRENGTH_LO_SHIFT 8
687#define DRIVE_STRENGTH_HI_SHIFT 12
688#define DRIVE_STRENGTH_MASK 0x0000FF00
689
690#define DS(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
691 ((hi) << DRIVE_STRENGTH_HI_SHIFT))
692#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)
693#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)
694
695#define GPI 0x1 /* Not GPO */
696#define GPO 0x2 /* Not GPI */
697#define SLEW 0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */
698#define SLEWLPC 0x8 /* Has Slew Control, SRCNT.3 */
699
700struct npcm7xx_pincfg {
701 int flag;
702 int fn0, reg0, bit0;
703 int fn1, reg1, bit1;
704 int fn2, reg2, bit2;
705};
706
707static const struct npcm7xx_pincfg pincfgs[] = {
708 /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */
709 NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
710 NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)),
711 NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)),
712 NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
713 NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
714 NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
715 NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
716 NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
717 NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DS(8, 12)),
718 NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DS(8, 12)),
719 NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)),
720 NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)),
721 NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
722 NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
723 NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
724 NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
725 NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)),
726 NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DS(8, 12)),
727 NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)),
728 NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)),
729 NPCM7XX_PINCFG(20, hgpio0, MFSEL2, 24, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, 0),
730 NPCM7XX_PINCFG(21, hgpio1, MFSEL2, 25, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, 0),
731 NPCM7XX_PINCFG(22, hgpio2, MFSEL2, 26, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, 0),
732 NPCM7XX_PINCFG(23, hgpio3, MFSEL2, 27, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, 0),
733 NPCM7XX_PINCFG(24, hgpio4, MFSEL2, 28, ioxh, MFSEL3, 18, none, NONE, 0, DS(8, 12)),
734 NPCM7XX_PINCFG(25, hgpio5, MFSEL2, 29, ioxh, MFSEL3, 18, none, NONE, 0, DS(8, 12)),
735 NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
736 NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
737 NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
738 NPCM7XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
739 NPCM7XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),
740 NPCM7XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),
741
742 NPCM7XX_PINCFG(32, spi0cs1, MFSEL1, 3, none, NONE, 0, none, NONE, 0, 0),
743 NPCM7XX_PINCFG(33, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
744 NPCM7XX_PINCFG(34, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
745 NPCM7XX_PINCFG(37, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),
746 NPCM7XX_PINCFG(38, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),
747 NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
748 NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
749 NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0),
750 NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DS(2, 4) | GPO),
751 NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
752 NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
753 NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0),
754 NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)),
755 NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)),
756 NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO),
757 NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0),
758 NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
759 NPCM7XX_PINCFG(51, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
760 NPCM7XX_PINCFG(52, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
761 NPCM7XX_PINCFG(53, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
762 NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
763 NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
764 NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0),
765 NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)),
766 NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)),
767 NPCM7XX_PINCFG(59, hgpio6, MFSEL2, 30, smb3d, I2CSEGSEL, 13, none, NONE, 0, 0),
768 NPCM7XX_PINCFG(60, hgpio7, MFSEL2, 31, smb3d, I2CSEGSEL, 13, none, NONE, 0, 0),
769 NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO),
770 NPCM7XX_PINCFG(62, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
771 NPCM7XX_PINCFG(63, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
772
773 NPCM7XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, 0),
774 NPCM7XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, 0),
775 NPCM7XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, 0),
776 NPCM7XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, 0),
777 NPCM7XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, 0),
778 NPCM7XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, 0),
779 NPCM7XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, 0),
780 NPCM7XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, 0),
781 NPCM7XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, 0),
782 NPCM7XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, 0),
783 NPCM7XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, 0),
784 NPCM7XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, 0),
785 NPCM7XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, 0),
786 NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0),
787 NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0),
788 NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0),
789 NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DS(4, 8)),
790 NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DS(4, 8)),
791 NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DS(4, 8)),
792 NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DS(4, 8)),
793 NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
794 NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
795 NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
796 NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
797 NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
798 NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
799 NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0),
800 NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)),
801 NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)),
802 NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
803 NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
804 NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
805
806 NPCM7XX_PINCFG(96, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
807 NPCM7XX_PINCFG(97, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
808 NPCM7XX_PINCFG(98, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
809 NPCM7XX_PINCFG(99, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
810 NPCM7XX_PINCFG(100, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
811 NPCM7XX_PINCFG(101, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
812 NPCM7XX_PINCFG(102, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
813 NPCM7XX_PINCFG(103, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
814 NPCM7XX_PINCFG(104, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
815 NPCM7XX_PINCFG(105, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
816 NPCM7XX_PINCFG(106, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
817 NPCM7XX_PINCFG(107, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
818 NPCM7XX_PINCFG(108, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),
819 NPCM7XX_PINCFG(109, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),
820 NPCM7XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
821 NPCM7XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
822 NPCM7XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
823 NPCM7XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
824 NPCM7XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),
825 NPCM7XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),
826 NPCM7XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),
827 NPCM7XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),
828 NPCM7XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),
829 NPCM7XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),
830 NPCM7XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),
831 NPCM7XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),
832 NPCM7XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),
833 NPCM7XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),
834 NPCM7XX_PINCFG(124, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),
835 NPCM7XX_PINCFG(125, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),
836 NPCM7XX_PINCFG(126, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),
837 NPCM7XX_PINCFG(127, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),
838
839 NPCM7XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),
840 NPCM7XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),
841 NPCM7XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),
842 NPCM7XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),
843 NPCM7XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
844 NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
845 NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
846 NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
847 NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
848 NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
849 NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
850 NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
851 NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
852 NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0),
853 NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
854 NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0),
855 NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)),
856 NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DS(4, 8)),
857 NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DS(4, 8)),
858 NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DS(4, 8)),
859 NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
860 NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
861 NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
862 NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
863 NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
864 NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */
865 NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
866 NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */
867 NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
868 NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
869 NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
870 NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
871
872 NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
873 NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DS(8, 12)),
874 NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DS(8, 12)),
875 NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
876 NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
877 NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
878 NPCM7XX_PINCFG(166, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
879 NPCM7XX_PINCFG(167, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
880 NPCM7XX_PINCFG(168, lpcclk, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL3, 16, 0),
881 NPCM7XX_PINCFG(169, scipme, MFSEL3, 0, none, NONE, 0, none, NONE, 0, 0),
882 NPCM7XX_PINCFG(170, sci, MFSEL1, 22, none, NONE, 0, none, NONE, 0, 0),
883 NPCM7XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
884 NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
885 NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
886 NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
887 NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)),
888 NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)),
889 NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)),
890 NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
891 NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
892 NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
893 NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
894 NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
895 NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
896 NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
897 NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
898 NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12)),
899 NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)),
900 NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DS(8, 12) | SLEW),
901 NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DS(8, 12) | SLEW),
902 NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DS(2, 4)),
903 NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */
904
905 NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */
906 NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
907 NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
908 NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
909 NPCM7XX_PINCFG(196, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
910 NPCM7XX_PINCFG(197, smb0den, I2CSEGSEL, 22, none, NONE, 0, none, NONE, 0, SLEW),
911 NPCM7XX_PINCFG(198, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),
912 NPCM7XX_PINCFG(199, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),
913 NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
914 NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
915 NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
916 NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DS(8, 12)),
917 NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
918 NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
919 NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)),
920 NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)),
921 NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
922 NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
923 NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
924 NPCM7XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
925 NPCM7XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
926 NPCM7XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
927 NPCM7XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
928 NPCM7XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
929 NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
930 NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
931 NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0),
932 NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)),
933 NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
934 NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
935 NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
936 NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
937
938 NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW),
939 NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
940 NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
941 NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
942 NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
943 NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
944 NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
945 NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DS(8, 12)),
946 NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */
947 NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
948 NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */
949};
950
951#define NPCM7XX_PIN(a, b) { .number = a, .name = b }
952struct npcm7xx_pin_desc {
953 unsigned int number;
954 const char *name;
955};
956
957/* number, name, drv_data */
958static const struct npcm7xx_pin_desc npcm7xx_pins[] = {
959 NPCM7XX_PIN(0, "GPIO0/IOX1DI"),
960 NPCM7XX_PIN(1, "GPIO1/IOX1LD"),
961 NPCM7XX_PIN(2, "GPIO2/IOX1CK"),
962 NPCM7XX_PIN(3, "GPIO3/IOX1D0"),
963 NPCM7XX_PIN(4, "GPIO4/IOX2DI/SMB1DSDA"),
964 NPCM7XX_PIN(5, "GPIO5/IOX2LD/SMB1DSCL"),
965 NPCM7XX_PIN(6, "GPIO6/IOX2CK/SMB2DSDA"),
966 NPCM7XX_PIN(7, "GPIO7/IOX2D0/SMB2DSCL"),
967 NPCM7XX_PIN(8, "GPIO8/LKGPO1"),
968 NPCM7XX_PIN(9, "GPIO9/LKGPO2"),
969 NPCM7XX_PIN(10, "GPIO10/IOXHLD"),
970 NPCM7XX_PIN(11, "GPIO11/IOXHCK"),
971 NPCM7XX_PIN(12, "GPIO12/GSPICK/SMB5BSCL"),
972 NPCM7XX_PIN(13, "GPIO13/GSPIDO/SMB5BSDA"),
973 NPCM7XX_PIN(14, "GPIO14/GSPIDI/SMB5CSCL"),
974 NPCM7XX_PIN(15, "GPIO15/GSPICS/SMB5CSDA"),
975 NPCM7XX_PIN(16, "GPIO16/LKGPO0"),
976 NPCM7XX_PIN(17, "GPIO17/PSPI2DI/SMB4DEN"),
977 NPCM7XX_PIN(18, "GPIO18/PSPI2D0/SMB4BSDA"),
978 NPCM7XX_PIN(19, "GPIO19/PSPI2CK/SMB4BSCL"),
979 NPCM7XX_PIN(20, "GPIO20/SMB4CSDA/SMB15SDA"),
980 NPCM7XX_PIN(21, "GPIO21/SMB4CSCL/SMB15SCL"),
981 NPCM7XX_PIN(22, "GPIO22/SMB4DSDA/SMB14SDA"),
982 NPCM7XX_PIN(23, "GPIO23/SMB4DSCL/SMB14SCL"),
983 NPCM7XX_PIN(24, "GPIO24/IOXHDO"),
984 NPCM7XX_PIN(25, "GPIO25/IOXHDI"),
985 NPCM7XX_PIN(26, "GPIO26/SMB5SDA"),
986 NPCM7XX_PIN(27, "GPIO27/SMB5SCL"),
987 NPCM7XX_PIN(28, "GPIO28/SMB4SDA"),
988 NPCM7XX_PIN(29, "GPIO29/SMB4SCL"),
989 NPCM7XX_PIN(30, "GPIO30/SMB3SDA"),
990 NPCM7XX_PIN(31, "GPIO31/SMB3SCL"),
991
992 NPCM7XX_PIN(32, "GPIO32/nSPI0CS1"),
993 NPCM7XX_PIN(33, "SPI0D2"),
994 NPCM7XX_PIN(34, "SPI0D3"),
995 NPCM7XX_PIN(35, "NA"),
996 NPCM7XX_PIN(36, "NA"),
997 NPCM7XX_PIN(37, "GPIO37/SMB3CSDA"),
998 NPCM7XX_PIN(38, "GPIO38/SMB3CSCL"),
999 NPCM7XX_PIN(39, "GPIO39/SMB3BSDA"),
1000 NPCM7XX_PIN(40, "GPIO40/SMB3BSCL"),
1001 NPCM7XX_PIN(41, "GPIO41/BSPRXD"),
1002 NPCM7XX_PIN(42, "GPO42/BSPTXD/STRAP11"),
1003 NPCM7XX_PIN(43, "GPIO43/RXD1/JTMS2/BU1RXD"),
1004 NPCM7XX_PIN(44, "GPIO44/nCTS1/JTDI2/BU1CTS"),
1005 NPCM7XX_PIN(45, "GPIO45/nDCD1/JTDO2"),
1006 NPCM7XX_PIN(46, "GPIO46/nDSR1/JTCK2"),
1007 NPCM7XX_PIN(47, "GPIO47/nRI1/JCP_RDY2"),
1008 NPCM7XX_PIN(48, "GPIO48/TXD2/BSPTXD"),
1009 NPCM7XX_PIN(49, "GPIO49/RXD2/BSPRXD"),
1010 NPCM7XX_PIN(50, "GPIO50/nCTS2"),
1011 NPCM7XX_PIN(51, "GPO51/nRTS2/STRAP2"),
1012 NPCM7XX_PIN(52, "GPIO52/nDCD2"),
1013 NPCM7XX_PIN(53, "GPO53/nDTR2_BOUT2/STRAP1"),
1014 NPCM7XX_PIN(54, "GPIO54/nDSR2"),
1015 NPCM7XX_PIN(55, "GPIO55/nRI2"),
1016 NPCM7XX_PIN(56, "GPIO56/R1RXERR"),
1017 NPCM7XX_PIN(57, "GPIO57/R1MDC"),
1018 NPCM7XX_PIN(58, "GPIO58/R1MDIO"),
1019 NPCM7XX_PIN(59, "GPIO59/SMB3DSDA"),
1020 NPCM7XX_PIN(60, "GPIO60/SMB3DSCL"),
1021 NPCM7XX_PIN(61, "GPO61/nDTR1_BOUT1/STRAP6"),
1022 NPCM7XX_PIN(62, "GPO62/nRTST1/STRAP5"),
1023 NPCM7XX_PIN(63, "GPO63/TXD1/STRAP4"),
1024
1025 NPCM7XX_PIN(64, "GPIO64/FANIN0"),
1026 NPCM7XX_PIN(65, "GPIO65/FANIN1"),
1027 NPCM7XX_PIN(66, "GPIO66/FANIN2"),
1028 NPCM7XX_PIN(67, "GPIO67/FANIN3"),
1029 NPCM7XX_PIN(68, "GPIO68/FANIN4"),
1030 NPCM7XX_PIN(69, "GPIO69/FANIN5"),
1031 NPCM7XX_PIN(70, "GPIO70/FANIN6"),
1032 NPCM7XX_PIN(71, "GPIO71/FANIN7"),
1033 NPCM7XX_PIN(72, "GPIO72/FANIN8"),
1034 NPCM7XX_PIN(73, "GPIO73/FANIN9"),
1035 NPCM7XX_PIN(74, "GPIO74/FANIN10"),
1036 NPCM7XX_PIN(75, "GPIO75/FANIN11"),
1037 NPCM7XX_PIN(76, "GPIO76/FANIN12"),
1038 NPCM7XX_PIN(77, "GPIO77/FANIN13"),
1039 NPCM7XX_PIN(78, "GPIO78/FANIN14"),
1040 NPCM7XX_PIN(79, "GPIO79/FANIN15"),
1041 NPCM7XX_PIN(80, "GPIO80/PWM0"),
1042 NPCM7XX_PIN(81, "GPIO81/PWM1"),
1043 NPCM7XX_PIN(82, "GPIO82/PWM2"),
1044 NPCM7XX_PIN(83, "GPIO83/PWM3"),
1045 NPCM7XX_PIN(84, "GPIO84/R2TXD0"),
1046 NPCM7XX_PIN(85, "GPIO85/R2TXD1"),
1047 NPCM7XX_PIN(86, "GPIO86/R2TXEN"),
1048 NPCM7XX_PIN(87, "GPIO87/R2RXD0"),
1049 NPCM7XX_PIN(88, "GPIO88/R2RXD1"),
1050 NPCM7XX_PIN(89, "GPIO89/R2CRSDV"),
1051 NPCM7XX_PIN(90, "GPIO90/R2RXERR"),
1052 NPCM7XX_PIN(91, "GPIO91/R2MDC"),
1053 NPCM7XX_PIN(92, "GPIO92/R2MDIO"),
1054 NPCM7XX_PIN(93, "GPIO93/GA20/SMB5DSCL"),
1055 NPCM7XX_PIN(94, "GPIO94/nKBRST/SMB5DSDA"),
1056 NPCM7XX_PIN(95, "GPIO95/nLRESET/nESPIRST"),
1057
1058 NPCM7XX_PIN(96, "GPIO96/RG1TXD0"),
1059 NPCM7XX_PIN(97, "GPIO97/RG1TXD1"),
1060 NPCM7XX_PIN(98, "GPIO98/RG1TXD2"),
1061 NPCM7XX_PIN(99, "GPIO99/RG1TXD3"),
1062 NPCM7XX_PIN(100, "GPIO100/RG1TXC"),
1063 NPCM7XX_PIN(101, "GPIO101/RG1TXCTL"),
1064 NPCM7XX_PIN(102, "GPIO102/RG1RXD0"),
1065 NPCM7XX_PIN(103, "GPIO103/RG1RXD1"),
1066 NPCM7XX_PIN(104, "GPIO104/RG1RXD2"),
1067 NPCM7XX_PIN(105, "GPIO105/RG1RXD3"),
1068 NPCM7XX_PIN(106, "GPIO106/RG1RXC"),
1069 NPCM7XX_PIN(107, "GPIO107/RG1RXCTL"),
1070 NPCM7XX_PIN(108, "GPIO108/RG1MDC"),
1071 NPCM7XX_PIN(109, "GPIO109/RG1MDIO"),
1072 NPCM7XX_PIN(110, "GPIO110/RG2TXD0/DDRV0"),
1073 NPCM7XX_PIN(111, "GPIO111/RG2TXD1/DDRV1"),
1074 NPCM7XX_PIN(112, "GPIO112/RG2TXD2/DDRV2"),
1075 NPCM7XX_PIN(113, "GPIO113/RG2TXD3/DDRV3"),
1076 NPCM7XX_PIN(114, "GPIO114/SMB0SCL"),
1077 NPCM7XX_PIN(115, "GPIO115/SMB0SDA"),
1078 NPCM7XX_PIN(116, "GPIO116/SMB1SCL"),
1079 NPCM7XX_PIN(117, "GPIO117/SMB1SDA"),
1080 NPCM7XX_PIN(118, "GPIO118/SMB2SCL"),
1081 NPCM7XX_PIN(119, "GPIO119/SMB2SDA"),
1082 NPCM7XX_PIN(120, "GPIO120/SMB2CSDA"),
1083 NPCM7XX_PIN(121, "GPIO121/SMB2CSCL"),
1084 NPCM7XX_PIN(122, "GPIO122/SMB2BSDA"),
1085 NPCM7XX_PIN(123, "GPIO123/SMB2BSCL"),
1086 NPCM7XX_PIN(124, "GPIO124/SMB1CSDA"),
1087 NPCM7XX_PIN(125, "GPIO125/SMB1CSCL"),
1088 NPCM7XX_PIN(126, "GPIO126/SMB1BSDA"),
1089 NPCM7XX_PIN(127, "GPIO127/SMB1BSCL"),
1090
1091 NPCM7XX_PIN(128, "GPIO128/SMB8SCL"),
1092 NPCM7XX_PIN(129, "GPIO129/SMB8SDA"),
1093 NPCM7XX_PIN(130, "GPIO130/SMB9SCL"),
1094 NPCM7XX_PIN(131, "GPIO131/SMB9SDA"),
1095 NPCM7XX_PIN(132, "GPIO132/SMB10SCL"),
1096 NPCM7XX_PIN(133, "GPIO133/SMB10SDA"),
1097 NPCM7XX_PIN(134, "GPIO134/SMB11SCL"),
1098 NPCM7XX_PIN(135, "GPIO135/SMB11SDA"),
1099 NPCM7XX_PIN(136, "GPIO136/SD1DT0"),
1100 NPCM7XX_PIN(137, "GPIO137/SD1DT1"),
1101 NPCM7XX_PIN(138, "GPIO138/SD1DT2"),
1102 NPCM7XX_PIN(139, "GPIO139/SD1DT3"),
1103 NPCM7XX_PIN(140, "GPIO140/SD1CLK"),
1104 NPCM7XX_PIN(141, "GPIO141/SD1WP"),
1105 NPCM7XX_PIN(142, "GPIO142/SD1CMD"),
1106 NPCM7XX_PIN(143, "GPIO143/SD1CD/SD1PWR"),
1107 NPCM7XX_PIN(144, "GPIO144/PWM4"),
1108 NPCM7XX_PIN(145, "GPIO145/PWM5"),
1109 NPCM7XX_PIN(146, "GPIO146/PWM6"),
1110 NPCM7XX_PIN(147, "GPIO147/PWM7"),
1111 NPCM7XX_PIN(148, "GPIO148/MMCDT4"),
1112 NPCM7XX_PIN(149, "GPIO149/MMCDT5"),
1113 NPCM7XX_PIN(150, "GPIO150/MMCDT6"),
1114 NPCM7XX_PIN(151, "GPIO151/MMCDT7"),
1115 NPCM7XX_PIN(152, "GPIO152/MMCCLK"),
1116 NPCM7XX_PIN(153, "GPIO153/MMCWP"),
1117 NPCM7XX_PIN(154, "GPIO154/MMCCMD"),
1118 NPCM7XX_PIN(155, "GPIO155/nMMCCD/nMMCRST"),
1119 NPCM7XX_PIN(156, "GPIO156/MMCDT0"),
1120 NPCM7XX_PIN(157, "GPIO157/MMCDT1"),
1121 NPCM7XX_PIN(158, "GPIO158/MMCDT2"),
1122 NPCM7XX_PIN(159, "GPIO159/MMCDT3"),
1123
1124 NPCM7XX_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT"),
1125 NPCM7XX_PIN(161, "GPIO161/nLFRAME/nESPICS"),
1126 NPCM7XX_PIN(162, "GPIO162/SERIRQ"),
1127 NPCM7XX_PIN(163, "GPIO163/LCLK/ESPICLK"),
1128 NPCM7XX_PIN(164, "GPIO164/LAD0/ESPI_IO0"/*dscnt6*/),
1129 NPCM7XX_PIN(165, "GPIO165/LAD1/ESPI_IO1"/*dscnt6*/),
1130 NPCM7XX_PIN(166, "GPIO166/LAD2/ESPI_IO2"/*dscnt6*/),
1131 NPCM7XX_PIN(167, "GPIO167/LAD3/ESPI_IO3"/*dscnt6*/),
1132 NPCM7XX_PIN(168, "GPIO168/nCLKRUN/nESPIALERT"),
1133 NPCM7XX_PIN(169, "GPIO169/nSCIPME"),
1134 NPCM7XX_PIN(170, "GPIO170/nSMI"),
1135 NPCM7XX_PIN(171, "GPIO171/SMB6SCL"),
1136 NPCM7XX_PIN(172, "GPIO172/SMB6SDA"),
1137 NPCM7XX_PIN(173, "GPIO173/SMB7SCL"),
1138 NPCM7XX_PIN(174, "GPIO174/SMB7SDA"),
1139 NPCM7XX_PIN(175, "GPIO175/PSPI1CK/FANIN19"),
1140 NPCM7XX_PIN(176, "GPIO176/PSPI1DO/FANIN18"),
1141 NPCM7XX_PIN(177, "GPIO177/PSPI1DI/FANIN17"),
1142 NPCM7XX_PIN(178, "GPIO178/R1TXD0"),
1143 NPCM7XX_PIN(179, "GPIO179/R1TXD1"),
1144 NPCM7XX_PIN(180, "GPIO180/R1TXEN"),
1145 NPCM7XX_PIN(181, "GPIO181/R1RXD0"),
1146 NPCM7XX_PIN(182, "GPIO182/R1RXD1"),
1147 NPCM7XX_PIN(183, "GPIO183/SPI3CK"),
1148 NPCM7XX_PIN(184, "GPO184/SPI3D0/STRAP9"),
1149 NPCM7XX_PIN(185, "GPO185/SPI3D1/STRAP10"),
1150 NPCM7XX_PIN(186, "GPIO186/nSPI3CS0"),
1151 NPCM7XX_PIN(187, "GPIO187/nSPI3CS1"),
1152 NPCM7XX_PIN(188, "GPIO188/SPI3D2/nSPI3CS2"),
1153 NPCM7XX_PIN(189, "GPIO189/SPI3D3/nSPI3CS3"),
1154 NPCM7XX_PIN(190, "GPIO190/nPRD_SMI"),
1155 NPCM7XX_PIN(191, "GPIO191"),
1156
1157 NPCM7XX_PIN(192, "GPIO192"),
1158 NPCM7XX_PIN(193, "GPIO193/R1CRSDV"),
1159 NPCM7XX_PIN(194, "GPIO194/SMB0BSCL"),
1160 NPCM7XX_PIN(195, "GPIO195/SMB0BSDA"),
1161 NPCM7XX_PIN(196, "GPIO196/SMB0CSCL"),
1162 NPCM7XX_PIN(197, "GPIO197/SMB0DEN"),
1163 NPCM7XX_PIN(198, "GPIO198/SMB0DSDA"),
1164 NPCM7XX_PIN(199, "GPIO199/SMB0DSCL"),
1165 NPCM7XX_PIN(200, "GPIO200/R2CK"),
1166 NPCM7XX_PIN(201, "GPIO201/R1CK"),
1167 NPCM7XX_PIN(202, "GPIO202/SMB0CSDA"),
1168 NPCM7XX_PIN(203, "GPIO203/FANIN16"),
1169 NPCM7XX_PIN(204, "GPIO204/DDC2SCL"),
1170 NPCM7XX_PIN(205, "GPIO205/DDC2SDA"),
1171 NPCM7XX_PIN(206, "GPIO206/HSYNC2"),
1172 NPCM7XX_PIN(207, "GPIO207/VSYNC2"),
1173 NPCM7XX_PIN(208, "GPIO208/RG2TXC/DVCK"),
1174 NPCM7XX_PIN(209, "GPIO209/RG2TXCTL/DDRV4"),
1175 NPCM7XX_PIN(210, "GPIO210/RG2RXD0/DDRV5"),
1176 NPCM7XX_PIN(211, "GPIO211/RG2RXD1/DDRV6"),
1177 NPCM7XX_PIN(212, "GPIO212/RG2RXD2/DDRV7"),
1178 NPCM7XX_PIN(213, "GPIO213/RG2RXD3/DDRV8"),
1179 NPCM7XX_PIN(214, "GPIO214/RG2RXC/DDRV9"),
1180 NPCM7XX_PIN(215, "GPIO215/RG2RXCTL/DDRV10"),
1181 NPCM7XX_PIN(216, "GPIO216/RG2MDC/DDRV11"),
1182 NPCM7XX_PIN(217, "GPIO217/RG2MDIO/DVHSYNC"),
1183 NPCM7XX_PIN(218, "GPIO218/nWDO1"),
1184 NPCM7XX_PIN(219, "GPIO219/nWDO2"),
1185 NPCM7XX_PIN(220, "GPIO220/SMB12SCL"),
1186 NPCM7XX_PIN(221, "GPIO221/SMB12SDA"),
1187 NPCM7XX_PIN(222, "GPIO222/SMB13SCL"),
1188 NPCM7XX_PIN(223, "GPIO223/SMB13SDA"),
1189 NPCM7XX_PIN(224, "GPIO224/SPIXCK"),
1190 NPCM7XX_PIN(225, "GPO225/SPIXD0/STRAP12"),
1191 NPCM7XX_PIN(226, "GPO226/SPIXD1/STRAP13"),
1192 NPCM7XX_PIN(227, "GPIO227/nSPIXCS0"),
1193 NPCM7XX_PIN(228, "GPIO228/nSPIXCS1"),
1194 NPCM7XX_PIN(229, "GPO229/SPIXD2/STRAP3"),
1195 NPCM7XX_PIN(230, "GPIO230/SPIXD3"),
1196 NPCM7XX_PIN(231, "GPIO231/nCLKREQ"),
1197 NPCM7XX_PIN(232, "NA"),
1198 NPCM7XX_PIN(233, "NA"),
1199 NPCM7XX_PIN(234, "NA"),
1200 NPCM7XX_PIN(235, "NA"),
1201 NPCM7XX_PIN(236, "NA"),
1202 NPCM7XX_PIN(237, "NA"),
1203 NPCM7XX_PIN(238, "NA"),
1204 NPCM7XX_PIN(239, "NA"),
1205 NPCM7XX_PIN(240, "NA"),
1206 NPCM7XX_PIN(241, "NA"),
1207 NPCM7XX_PIN(242, "NA"),
1208 NPCM7XX_PIN(243, "NA"),
1209 NPCM7XX_PIN(244, "NA"),
1210 NPCM7XX_PIN(245, "NA"),
1211 NPCM7XX_PIN(246, "NA"),
1212 NPCM7XX_PIN(247, "NA"),
1213 NPCM7XX_PIN(248, "NA"),
1214 NPCM7XX_PIN(249, "NA"),
1215 NPCM7XX_PIN(250, "NA"),
1216 NPCM7XX_PIN(251, "NA"),
1217 NPCM7XX_PIN(252, "NA"),
1218 NPCM7XX_PIN(253, "NA"),
1219 NPCM7XX_PIN(254, "NA"),
1220 NPCM7XX_PIN(255, "GPI255/DACOSEL"),
1221};
1222
1223struct npcm7xx_pinctrl_priv {
1224 void __iomem *gpio_base;
1225 struct regmap *gcr_regmap;
1226 struct regmap *rst_regmap;
1227};
1228
1229static int npcm7xx_pinctrl_probe(struct udevice *dev)
1230{
1231 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1232
1233 priv->gpio_base = dev_read_addr_ptr(dev);
1234 if (!priv->gpio_base)
1235 return -EINVAL;
1236
1237 priv->gcr_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-gcr");
1238 if (IS_ERR(priv->gcr_regmap))
1239 return -EINVAL;
1240
1241 priv->rst_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-rst");
1242 if (IS_ERR(priv->rst_regmap))
1243 return -EINVAL;
1244
1245 return 0;
1246}
1247
1248/* Enable mode in pin group */
1249static void npcm7xx_setfunc(struct udevice *dev, const int *pin,
1250 int pin_number, int mode)
1251{
1252 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1253 const struct npcm7xx_pincfg *cfg;
1254 int i;
1255
1256 for (i = 0 ; i < pin_number ; i++) {
1257 cfg = &pincfgs[pin[i]];
1258 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) {
1259 if (cfg->reg0) {
1260 if (cfg->fn0 == mode)
1261 regmap_update_bits(priv->gcr_regmap, cfg->reg0, BIT(cfg->bit0), BIT(cfg->bit0));
1262 else
1263 regmap_update_bits(priv->gcr_regmap, cfg->reg0, BIT(cfg->bit0), 0);
1264 }
1265 if (cfg->reg1) {
1266 if (cfg->fn1 == mode)
1267 regmap_update_bits(priv->gcr_regmap, cfg->reg1, BIT(cfg->bit1), BIT(cfg->bit1));
1268 else
1269 regmap_update_bits(priv->gcr_regmap, cfg->reg1, BIT(cfg->bit1), 0);
1270 }
1271 if (cfg->reg2) {
1272 if (cfg->fn2 == mode)
1273 regmap_update_bits(priv->gcr_regmap, cfg->reg2, BIT(cfg->bit2), BIT(cfg->bit2));
1274 else
1275 regmap_update_bits(priv->gcr_regmap, cfg->reg2, BIT(cfg->bit2), 0);
1276 }
1277 }
1278 }
1279}
1280
1281static int npcm7xx_get_pins_count(struct udevice *dev)
1282{
1283 return ARRAY_SIZE(npcm7xx_pins);
1284}
1285
1286static const char *npcm7xx_get_pin_name(struct udevice *dev,
1287 unsigned int selector)
1288{
1289 return npcm7xx_pins[selector].name;
1290}
1291
1292static int npcm7xx_get_groups_count(struct udevice *dev)
1293{
1294 return ARRAY_SIZE(npcm7xx_groups);
1295}
1296
1297static const char *npcm7xx_get_group_name(struct udevice *dev,
1298 unsigned int selector)
1299{
1300 return npcm7xx_groups[selector].name;
1301}
1302
1303static int npcm7xx_get_functions_count(struct udevice *dev)
1304{
1305 return ARRAY_SIZE(npcm7xx_funcs);
1306}
1307
1308static const char *npcm7xx_get_function_name(struct udevice *dev,
1309 unsigned int selector)
1310{
1311 return npcm7xx_funcs[selector].name;
1312}
1313
1314static int npcm7xx_pinmux_set(struct udevice *dev,
1315 unsigned int group,
1316 unsigned int function)
1317{
1318 dev_dbg(dev, "set_mux: %d, %d[%s]\n", function, group,
1319 npcm7xx_groups[group].name);
1320
1321 npcm7xx_setfunc(dev, npcm7xx_groups[group].pins,
1322 npcm7xx_groups[group].npins, group);
1323
1324 return 0;
1325}
1326
1327#if CONFIG_IS_ENABLED(PINCONF)
1328
1329#define PIN_CONFIG_PERSIST_STATE (PIN_CONFIG_END + 1)
1330#define PIN_CONFIG_POLARITY_STATE (PIN_CONFIG_END + 2)
1331#define PIN_CONFIG_EVENT_CLEAR (PIN_CONFIG_END + 3)
1332
1333static const struct pinconf_param npcm7xx_conf_params[] = {
1334 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
1335 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
1336 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
1337 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
1338 { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
1339 { "output-high", PIN_CONFIG_OUTPUT, 1, },
1340 { "output-low", PIN_CONFIG_OUTPUT, 0, },
1341 { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 1 },
1342 { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 1 },
1343 { "persist-enable", PIN_CONFIG_PERSIST_STATE, 1 },
1344 { "persist-disable", PIN_CONFIG_PERSIST_STATE, 0 },
1345 { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
1346 { "active-high", PIN_CONFIG_POLARITY_STATE, 0 },
1347 { "active-low", PIN_CONFIG_POLARITY_STATE, 1 },
1348 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
1349 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0},
1350 { "event-clear", PIN_CONFIG_EVENT_CLEAR, 0},
1351};
1352
1353static bool is_gpio_persist(struct udevice *dev, u8 bank)
1354{
1355 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1356 u32 value, tmp;
1357
1358 u8 offset = bank + GPIOX_MODULE_RESET;
1359 u32 mask = 1 << offset;
1360
1361 regmap_read(priv->gcr_regmap, NPCM7XX_GCR_RESSR, &value);
1362 if (value == 0) {
1363 regmap_read(priv->gcr_regmap, NPCM7XX_GCR_INTCR2, &tmp);
1364 value = ~tmp;
1365 }
1366
1367 dev_dbg(dev, "reboot reason: 0x%x\n", value);
1368
1369 if (value & CORST)
1370 regmap_read(priv->rst_regmap, NPCM7XX_RST_CORSTC, &tmp);
1371 else if (value & WD0RST)
1372 regmap_read(priv->rst_regmap, NPCM7XX_RST_WD0RCR, &tmp);
1373 else if (value & WD1RST)
1374 regmap_read(priv->rst_regmap, NPCM7XX_RST_WD1RCR, &tmp);
1375 else if (value & WD2RST)
1376 regmap_read(priv->rst_regmap, NPCM7XX_RST_WD2RCR, &tmp);
1377 else
1378 return false;
1379
1380 return !((tmp & mask) >> offset);
1381}
1382
1383static int npcm7xx_gpio_reset_persist(struct udevice *dev, unsigned int banknum, int enable)
1384{
1385 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1386 u32 num = GPIOX_MODULE_RESET + banknum;
1387
1388 dev_dbg(dev, "set gpio persist, bank %d, enable %d\n", banknum, enable);
1389
1390 if (enable) {
1391 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, 0);
1392 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, 0);
1393 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num) | CA9C_RESET, 0);
1394 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num) | CA9C_RESET, 0);
1395 } else {
1396 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
1397 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
1398 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
1399 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
1400 }
1401
1402 return 0;
1403}
1404
1405/* Set drive strength for a pin, if supported */
1406static int npcm7xx_set_drive_strength(struct udevice *dev,
1407 unsigned int pin, int nval)
1408{
1409 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1410 int bank = pin / NPCM7XX_GPIO_PER_BANK;
1411 int gpio = (pin % NPCM7XX_GPIO_PER_BITS);
1412 void __iomem *base = priv->gpio_base + (NPCM7XX_GPIO_BANK_OFFSET * bank);
1413 int v;
1414
1415 v = (pincfgs[pin].flag & DRIVE_STRENGTH_MASK);
1416 if (!nval || !v)
1417 return -ENOTSUPP;
1418
1419 if (DSLO(v) == nval) {
1420 dev_dbg(dev,
1421 "setting pin %d to low strength [%d]\n", pin, nval);
1422 clrbits_le32(base + NPCM7XX_GP_N_ODSC, BIT(gpio));
1423 return 0;
1424 } else if (DSHI(v) == nval) {
1425 dev_dbg(dev,
1426 "setting pin %d to high strength [%d]\n", pin, nval);
1427 setbits_le32(base + NPCM7XX_GP_N_ODSC, BIT(gpio));
1428 return 0;
1429 }
1430
1431 return -ENOTSUPP;
1432}
1433
1434/* Set slew rate of pin (high/low) */
1435static int npcm7xx_set_slew_rate(struct udevice *dev, unsigned int pin,
1436 int arg)
1437{
1438 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1439 int bank = pin / NPCM7XX_GPIO_PER_BANK;
1440 int gpio = (pin % NPCM7XX_GPIO_PER_BITS);
1441 void __iomem *base = priv->gpio_base + (NPCM7XX_GPIO_BANK_OFFSET * bank);
1442
1443 if (pincfgs[pin].flag & SLEW) {
1444 switch (arg) {
1445 case 0:
1446 dev_dbg(dev,
1447 "setting pin %d slew rate to low\n", pin);
1448 clrbits_le32(base + NPCM7XX_GP_N_OSRC, BIT(gpio));
1449 return 0;
1450 case 1:
1451 dev_dbg(dev,
1452 "setting pin %d slew rate to high\n", pin);
1453 setbits_le32(base + NPCM7XX_GP_N_OSRC, BIT(gpio));
1454 return 0;
1455 default:
1456 return -ENOTSUPP;
1457 }
1458 }
1459
1460 /* LPC Slew rate in SRCNT register */
1461 if (pincfgs[pin].flag & SLEWLPC) {
1462 switch (arg) {
1463 case 0:
1464 dev_dbg(dev,
1465 "setting LPC/ESPI(%d) slew rate to low\n", pin);
1466 regmap_update_bits(priv->gcr_regmap, NPCM7XX_GCR_SRCNT, SRCNT_ESPI, 0);
1467 return 0;
1468 case 1:
1469 dev_dbg(dev, "setting LPC/ESPI(%d) slew rate to high\n", pin);
1470 regmap_update_bits(priv->gcr_regmap, NPCM7XX_GCR_SRCNT, SRCNT_ESPI, SRCNT_ESPI);
1471 return 0;
1472 default:
1473 return -ENOTSUPP;
1474 }
1475 }
1476
1477 return -ENOTSUPP;
1478}
1479
1480static int npcm7xx_pinconf_set(struct udevice *dev, unsigned int pin,
1481 unsigned int param, unsigned int arg)
1482{
1483 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1484 int err = 0;
1485 int bank = pin / NPCM7XX_GPIO_PER_BANK;
1486 int gpio = (pin % NPCM7XX_GPIO_PER_BITS);
1487 void __iomem *base = priv->gpio_base + (0x1000 * bank);
1488
1489 npcm7xx_setfunc(dev, (const int *)&pin, 1, fn_gpio);
1490
1491 /* To prevent unexpected IRQ trap at verctor 00 in linux kernel */
1492 if (param == PIN_CONFIG_EVENT_CLEAR) {
1493 dev_dbg(dev, "set pin %d event clear\n", pin);
1494 clrbits_le32(base + NPCM7XX_GP_N_EVEN, BIT(gpio));
1495 setbits_le32(base + NPCM7XX_GP_N_EVST, BIT(gpio));
1496 return err;
1497 }
1498
1499 // allow set persist state disable
1500 if (param == PIN_CONFIG_PERSIST_STATE) {
1501 npcm7xx_gpio_reset_persist(dev, bank, arg);
1502 return err;
1503 }
1504
1505 if (is_gpio_persist(dev, bank))
1506 return err;
1507
1508 switch (param) {
1509 case PIN_CONFIG_BIAS_DISABLE:
1510 dev_dbg(dev, "set pin %d bias dsiable\n", pin);
1511 clrbits_le32(base + NPCM7XX_GP_N_PU, BIT(gpio));
1512 clrbits_le32(base + NPCM7XX_GP_N_PD, BIT(gpio));
1513 break;
1514 case PIN_CONFIG_BIAS_PULL_DOWN:
1515 dev_dbg(dev, "set pin %d bias pull down\n", pin);
1516 clrbits_le32(base + NPCM7XX_GP_N_PU, BIT(gpio));
1517 setbits_le32(base + NPCM7XX_GP_N_PD, BIT(gpio));
1518 break;
1519 case PIN_CONFIG_BIAS_PULL_UP:
1520 dev_dbg(dev, "set pin %d bias pull up\n", pin);
1521 setbits_le32(base + NPCM7XX_GP_N_PU, BIT(gpio));
1522 clrbits_le32(base + NPCM7XX_GP_N_PD, BIT(gpio));
1523 break;
1524 case PIN_CONFIG_INPUT_ENABLE:
1525 dev_dbg(dev, "set pin %d input enable\n", pin);
1526 setbits_le32(base + NPCM7XX_GP_N_OEC, BIT(gpio));
1527 setbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
1528 break;
1529 case PIN_CONFIG_OUTPUT_ENABLE:
1530 dev_dbg(dev, "set pin %d output enable\n", pin);
1531 clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
1532 setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
1533 case PIN_CONFIG_OUTPUT:
1534 dev_dbg(dev, "set pin %d output %d\n", pin, arg);
1535 clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
1536 setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
1537 if (arg)
1538 setbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio));
1539 else
1540 clrbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio));
1541 break;
1542 case PIN_CONFIG_DRIVE_PUSH_PULL:
1543 dev_dbg(dev, "set pin %d push pull\n", pin);
1544 clrbits_le32(base + NPCM7XX_GP_N_OTYP, BIT(gpio));
1545 break;
1546 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1547 dev_dbg(dev, "set pin %d open drain\n", pin);
1548 setbits_le32(base + NPCM7XX_GP_N_OTYP, BIT(gpio));
1549 break;
1550 case PIN_CONFIG_INPUT_DEBOUNCE:
1551 dev_dbg(dev, "set pin %d input debounce\n", pin);
1552 setbits_le32(base + NPCM7XX_GP_N_DBNC, BIT(gpio));
1553 break;
1554 case PIN_CONFIG_POLARITY_STATE:
1555 dev_dbg(dev, "set pin %d active %d\n", pin, arg);
1556 if (arg)
1557 setbits_le32(base + NPCM7XX_GP_N_POL, BIT(gpio));
1558 else
1559 clrbits_le32(base + NPCM7XX_GP_N_POL, BIT(gpio));
1560 break;
1561 case PIN_CONFIG_DRIVE_STRENGTH:
1562 dev_dbg(dev, "set pin %d driver strength %d\n", pin, arg);
1563 err = npcm7xx_set_drive_strength(dev, pin, arg);
1564 break;
1565 case PIN_CONFIG_SLEW_RATE:
1566 dev_dbg(dev, "set pin %d slew rate %d\n", pin, arg);
1567 err = npcm7xx_set_slew_rate(dev, pin, arg);
1568 break;
1569 default:
1570 err = -ENOTSUPP;
1571 }
1572 return err;
1573}
1574
1575#endif
1576
1577static struct pinctrl_ops npcm7xx_pinctrl_ops = {
1578 .set_state = pinctrl_generic_set_state,
1579 .get_pins_count = npcm7xx_get_pins_count,
1580 .get_pin_name = npcm7xx_get_pin_name,
1581 .get_groups_count = npcm7xx_get_groups_count,
1582 .get_group_name = npcm7xx_get_group_name,
1583 .get_functions_count = npcm7xx_get_functions_count,
1584 .get_function_name = npcm7xx_get_function_name,
1585 .pinmux_set = npcm7xx_pinmux_set,
1586 .pinmux_group_set = npcm7xx_pinmux_set,
1587#if CONFIG_IS_ENABLED(PINCONF)
1588 .pinconf_num_params = ARRAY_SIZE(npcm7xx_conf_params),
1589 .pinconf_params = npcm7xx_conf_params,
1590 .pinconf_set = npcm7xx_pinconf_set,
1591 .pinconf_group_set = npcm7xx_pinconf_set,
1592#endif
1593};
1594
1595static const struct udevice_id npcm7xx_pinctrl_ids[] = {
1596 { .compatible = "nuvoton,npcm750-pinctrl" },
1597 { }
1598};
1599
1600U_BOOT_DRIVER(pinctrl_npcm7xx) = {
1601 .name = "nuvoton_npcm7xx_pinctrl",
1602 .id = UCLASS_PINCTRL,
1603 .of_match = npcm7xx_pinctrl_ids,
1604 .priv_auto = sizeof(struct npcm7xx_pinctrl_priv),
1605 .ops = &npcm7xx_pinctrl_ops,
1606 .probe = npcm7xx_pinctrl_probe,
1607};