blob: a61eb5bd85c25d2c826322af7ea87dac0d92ee6c [file] [log] [blame]
Simon Glass8c501022019-12-06 21:41:54 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PCI emulation device for an x86 Power-Management Controller (PMC)
4 *
5 * Copyright 2019 Google LLC
6 * Written by Simon Glass <sjg@chromium.org>
7 */
8
9#include <common.h>
10#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Simon Glass8c501022019-12-06 21:41:54 -070012#include <pci.h>
13#include <asm/test.h>
14#include <power/acpi_pmc.h>
15
16/**
Simon Glassb75b15b2020-12-03 16:55:23 -070017 * struct pmc_emul_plat - platform data for this device
Simon Glass8c501022019-12-06 21:41:54 -070018 *
19 * @command: Current PCI command value
20 * @bar: Current base address values
21 */
Simon Glassb75b15b2020-12-03 16:55:23 -070022struct pmc_emul_plat {
Simon Glass8c501022019-12-06 21:41:54 -070023 u16 command;
24 u32 bar[6];
25};
26
27enum {
28 MEMMAP_SIZE = 0x80,
29};
30
31static struct pci_bar {
32 int type;
33 u32 size;
34} barinfo[] = {
35 { PCI_BASE_ADDRESS_MEM_TYPE_32, MEMMAP_SIZE },
36 { 0, 0 },
37 { 0, 0 },
38 { 0, 0 },
39 { PCI_BASE_ADDRESS_SPACE_IO, 256 },
40};
41
42struct pmc_emul_priv {
43 u8 regs[MEMMAP_SIZE];
44};
45
Simon Glass2a311e82020-01-27 08:49:37 -070046static int sandbox_pmc_emul_read_config(const struct udevice *emul, uint offset,
Simon Glass8c501022019-12-06 21:41:54 -070047 ulong *valuep, enum pci_size_t size)
48{
Simon Glassb75b15b2020-12-03 16:55:23 -070049 struct pmc_emul_plat *plat = dev_get_plat(emul);
Simon Glass8c501022019-12-06 21:41:54 -070050
51 switch (offset) {
52 case PCI_COMMAND:
53 *valuep = plat->command;
54 break;
55 case PCI_HEADER_TYPE:
56 *valuep = 0;
57 break;
58 case PCI_VENDOR_ID:
59 *valuep = SANDBOX_PCI_VENDOR_ID;
60 break;
61 case PCI_DEVICE_ID:
62 *valuep = SANDBOX_PCI_PMC_EMUL_ID;
63 break;
64 case PCI_CLASS_DEVICE:
65 if (size == PCI_SIZE_8) {
66 *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
67 } else {
68 *valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
69 SANDBOX_PCI_CLASS_SUB_CODE;
70 }
71 break;
72 case PCI_CLASS_CODE:
73 *valuep = SANDBOX_PCI_CLASS_CODE;
74 break;
75 case PCI_BASE_ADDRESS_0:
76 case PCI_BASE_ADDRESS_1:
77 case PCI_BASE_ADDRESS_2:
78 case PCI_BASE_ADDRESS_3:
79 case PCI_BASE_ADDRESS_4:
80 case PCI_BASE_ADDRESS_5: {
81 int barnum;
82 u32 *bar;
83
84 barnum = pci_offset_to_barnum(offset);
85 bar = &plat->bar[barnum];
86
87 *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
88 barinfo[barnum].size);
89 break;
90 }
91 case PCI_CAPABILITY_LIST:
92 *valuep = PCI_CAP_ID_PM_OFFSET;
93 break;
94 }
95
96 return 0;
97}
98
99static int sandbox_pmc_emul_write_config(struct udevice *emul, uint offset,
100 ulong value, enum pci_size_t size)
101{
Simon Glassb75b15b2020-12-03 16:55:23 -0700102 struct pmc_emul_plat *plat = dev_get_plat(emul);
Simon Glass8c501022019-12-06 21:41:54 -0700103
104 switch (offset) {
105 case PCI_COMMAND:
106 plat->command = value;
107 break;
108 case PCI_BASE_ADDRESS_0:
109 case PCI_BASE_ADDRESS_1: {
110 int barnum;
111 u32 *bar;
112
113 barnum = pci_offset_to_barnum(offset);
114 bar = &plat->bar[barnum];
115
116 debug("w bar %d=%lx\n", barnum, value);
117 *bar = value;
118 /* space indicator (bit#0) is read-only */
119 *bar |= barinfo[barnum].type;
120 break;
121 }
122 }
123
124 return 0;
125}
126
127static int sandbox_pmc_emul_find_bar(struct udevice *emul, unsigned int addr,
128 int *barnump, unsigned int *offsetp)
129{
Simon Glassb75b15b2020-12-03 16:55:23 -0700130 struct pmc_emul_plat *plat = dev_get_plat(emul);
Simon Glass8c501022019-12-06 21:41:54 -0700131 int barnum;
132
133 for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
134 unsigned int size = barinfo[barnum].size;
135 u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
136
137 if (addr >= base && addr < base + size) {
138 *barnump = barnum;
139 *offsetp = addr - base;
140 return 0;
141 }
142 }
143 *barnump = -1;
144
145 return -ENOENT;
146}
147
148static int sandbox_pmc_emul_read_io(struct udevice *dev, unsigned int addr,
149 ulong *valuep, enum pci_size_t size)
150{
151 unsigned int offset;
152 int barnum;
153 int ret;
154
155 ret = sandbox_pmc_emul_find_bar(dev, addr, &barnum, &offset);
156 if (ret)
157 return ret;
158
159 if (barnum == 4)
160 *valuep = offset;
161 else if (barnum == 0)
162 *valuep = offset;
163
164 return 0;
165}
166
167static int sandbox_pmc_emul_write_io(struct udevice *dev, unsigned int addr,
168 ulong value, enum pci_size_t size)
169{
170 unsigned int offset;
171 int barnum;
172 int ret;
173
174 ret = sandbox_pmc_emul_find_bar(dev, addr, &barnum, &offset);
175 if (ret)
176 return ret;
177
178 return 0;
179}
180
181static int sandbox_pmc_emul_map_physmem(struct udevice *dev,
182 phys_addr_t addr, unsigned long *lenp,
183 void **ptrp)
184{
185 struct pmc_emul_priv *priv = dev_get_priv(dev);
186 unsigned int offset, avail;
187 int barnum;
188 int ret;
189
190 ret = sandbox_pmc_emul_find_bar(dev, addr, &barnum, &offset);
191 if (ret)
192 return ret;
193
194 if (barnum == 0) {
195 *ptrp = priv->regs + offset;
196 avail = barinfo[0].size - offset;
197 if (avail > barinfo[0].size)
198 *lenp = 0;
199 else
200 *lenp = min(*lenp, (ulong)avail);
201
202 return 0;
203 }
204
205 return -ENOENT;
206}
207
208static int sandbox_pmc_probe(struct udevice *dev)
209{
210 struct pmc_emul_priv *priv = dev_get_priv(dev);
211 int i;
212
213 for (i = 0; i < MEMMAP_SIZE; i++)
214 priv->regs[i] = i;
215
216 return 0;
217}
218
219static struct dm_pci_emul_ops sandbox_pmc_emul_emul_ops = {
220 .read_config = sandbox_pmc_emul_read_config,
221 .write_config = sandbox_pmc_emul_write_config,
222 .read_io = sandbox_pmc_emul_read_io,
223 .write_io = sandbox_pmc_emul_write_io,
224 .map_physmem = sandbox_pmc_emul_map_physmem,
225};
226
227static const struct udevice_id sandbox_pmc_emul_ids[] = {
228 { .compatible = "sandbox,pmc-emul" },
229 { }
230};
231
232U_BOOT_DRIVER(sandbox_pmc_emul_emul) = {
233 .name = "sandbox_pmc_emul_emul",
234 .id = UCLASS_PCI_EMUL,
235 .of_match = sandbox_pmc_emul_ids,
236 .ops = &sandbox_pmc_emul_emul_ops,
237 .probe = sandbox_pmc_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700238 .priv_auto = sizeof(struct pmc_emul_priv),
Simon Glassb75b15b2020-12-03 16:55:23 -0700239 .plat_auto = sizeof(struct pmc_emul_plat),
Simon Glass8c501022019-12-06 21:41:54 -0700240};
241
242static struct pci_device_id sandbox_pmc_emul_supported[] = {
243 { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_PMC_EMUL_ID) },
244 {},
245};
246
247U_BOOT_PCI_DEVICE(sandbox_pmc_emul_emul, sandbox_pmc_emul_supported);