Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 2 | /* |
Marcel Ziswiler | 510c2dd | 2019-03-25 17:25:01 +0100 | [diff] [blame] | 3 | * Copyright 2015-2019 Toradex, Inc. |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 4 | * |
Marcel Ziswiler | d92dee5 | 2016-11-16 17:49:23 +0100 | [diff] [blame] | 5 | * Configuration settings for the Toradex VF50/VF61 modules. |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 6 | * |
| 7 | * Based on vf610twr.h: |
| 8 | * Copyright 2013 Freescale Semiconductor, Inc. |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
| 14 | #include <asm/arch/imx-regs.h> |
Marcel Ziswiler | 2e3b3d5 | 2019-03-25 17:25:02 +0100 | [diff] [blame^] | 15 | #include <linux/sizes.h> |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 16 | |
Gong Qianyu | 52de2e5 | 2015-10-26 19:47:42 +0800 | [diff] [blame] | 17 | #define CONFIG_SYS_FSL_CLK |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 18 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 19 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 20 | |
Stefan Agner | 1301175 | 2017-04-11 11:12:14 +0530 | [diff] [blame] | 21 | #ifdef CONFIG_VIDEO_FSL_DCU_FB |
Stefan Agner | 1301175 | 2017-04-11 11:12:14 +0530 | [diff] [blame] | 22 | #define CONFIG_SPLASH_SCREEN_ALIGN |
| 23 | #define CONFIG_VIDEO_LOGO |
| 24 | #define CONFIG_VIDEO_BMP_LOGO |
| 25 | #define CONFIG_SYS_FSL_DCU_LE |
| 26 | |
| 27 | #define CONFIG_SYS_DCU_ADDR DCU0_BASE_ADDR |
| 28 | #define DCU_LAYER_MAX_NUM 64 |
| 29 | #endif |
| 30 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 31 | /* Size of malloc() pool */ |
Marcel Ziswiler | 2e3b3d5 | 2019-03-25 17:25:02 +0100 | [diff] [blame^] | 32 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 33 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 34 | /* Allow to overwrite serial and ethaddr */ |
| 35 | #define CONFIG_ENV_OVERWRITE |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 36 | |
| 37 | /* NAND support */ |
Stefan Agner | 4ce682a | 2015-05-08 19:07:13 +0200 | [diff] [blame] | 38 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 39 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 40 | |
| 41 | #define CONFIG_IPADDR 192.168.10.2 |
| 42 | #define CONFIG_NETMASK 255.255.255.0 |
| 43 | #define CONFIG_SERVERIP 192.168.10.1 |
| 44 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 45 | #define CONFIG_LOADADDR 0x80008000 |
| 46 | #define CONFIG_FDTADDR 0x84000000 |
| 47 | |
| 48 | /* We boot from the gfxRAM area of the OCRAM. */ |
Stefan Agner | 1faaa3c | 2017-10-17 13:59:19 +0200 | [diff] [blame] | 49 | #define CONFIG_BOARD_SIZE_LIMIT 520192 |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 50 | |
| 51 | #define SD_BOOTCMD \ |
| 52 | "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ |
| 53 | "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \ |
| 54 | "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ |
| 55 | "load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \ |
| 56 | "load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \ |
Sanchayan Maity | a48b427 | 2016-12-02 14:28:27 +0530 | [diff] [blame] | 57 | "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 58 | |
| 59 | #define NFS_BOOTCMD \ |
| 60 | "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ |
| 61 | "nfsboot=run setup; " \ |
| 62 | "setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \ |
| 63 | "${setupargs} ${vidargs}; echo Booting from NFS...;" \ |
| 64 | "dhcp ${kernel_addr_r} && " \ |
| 65 | "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ |
Sanchayan Maity | a48b427 | 2016-12-02 14:28:27 +0530 | [diff] [blame] | 66 | "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 67 | |
| 68 | #define UBI_BOOTCMD \ |
| 69 | "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ |
| 70 | "ubi.fm_autoconvert=1\0" \ |
| 71 | "ubiboot=run setup; " \ |
| 72 | "setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \ |
| 73 | "${setupargs} ${vidargs}; echo Booting from NAND...; " \ |
Sanchayan Maity | 27e4e10 | 2016-11-25 16:19:17 +0530 | [diff] [blame] | 74 | "ubi part ubi && " \ |
| 75 | "ubi read ${kernel_addr_r} kernel && " \ |
| 76 | "ubi read ${fdt_addr_r} dtb && " \ |
Sanchayan Maity | a48b427 | 2016-12-02 14:28:27 +0530 | [diff] [blame] | 77 | "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 78 | |
| 79 | #define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot" |
| 80 | |
Sanchayan Maity | 7755e53 | 2015-04-17 18:56:42 +0530 | [diff] [blame] | 81 | #define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4" |
| 82 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 83 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 84 | "kernel_addr_r=0x82000000\0" \ |
| 85 | "fdt_addr_r=0x84000000\0" \ |
| 86 | "kernel_file=zImage\0" \ |
| 87 | "fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \ |
| 88 | "fdt_board=eval-v3\0" \ |
Sanchayan Maity | a48b427 | 2016-12-02 14:28:27 +0530 | [diff] [blame] | 89 | "fdt_fixup=;\0" \ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 90 | "defargs=\0" \ |
| 91 | "console=ttyLP0\0" \ |
| 92 | "setup=setenv setupargs " \ |
| 93 | "console=tty1 console=${console}" \ |
| 94 | ",${baudrate}n8 ${memargs}\0" \ |
| 95 | "setsdupdate=mmc rescan && set interface mmc && " \ |
| 96 | "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ |
| 97 | "source ${loadaddr}\0" \ |
| 98 | "setusbupdate=usb start && set interface usb && " \ |
| 99 | "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ |
| 100 | "source ${loadaddr}\0" \ |
| 101 | "setupdate=run setsdupdate || run setusbupdate\0" \ |
Tom Rini | 5ad8e11 | 2017-10-22 17:55:07 -0400 | [diff] [blame] | 102 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ |
Sanchayan Maity | 7755e53 | 2015-04-17 18:56:42 +0530 | [diff] [blame] | 103 | "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ |
Stefan Agner | 1301175 | 2017-04-11 11:12:14 +0530 | [diff] [blame] | 104 | "video-mode=dcufb:640x480-16@60,monitor=lcd\0" \ |
| 105 | "splashpos=m,m\0" \ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 106 | SD_BOOTCMD \ |
| 107 | NFS_BOOTCMD \ |
| 108 | UBI_BOOTCMD |
| 109 | |
| 110 | /* Miscellaneous configurable options */ |
Sanchayan Maity | 0d92de4 | 2015-06-08 12:40:41 +0530 | [diff] [blame] | 111 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 112 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 113 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 114 | #define CONFIG_SYS_MEMTEST_START 0x80010000 |
| 115 | #define CONFIG_SYS_MEMTEST_END 0x87C00000 |
| 116 | |
| 117 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
| 118 | #define CONFIG_SYS_HZ 1000 |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 119 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 120 | /* Physical memory map */ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 121 | #define PHYS_SDRAM (0x80000000) |
Marcel Ziswiler | 2e3b3d5 | 2019-03-25 17:25:02 +0100 | [diff] [blame^] | 122 | #define PHYS_SDRAM_SIZE (256 * SZ_1M) |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 123 | |
| 124 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
| 125 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
| 126 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
| 127 | |
| 128 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 129 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 130 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 131 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 132 | |
| 133 | /* Environment organization */ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 134 | #ifdef CONFIG_ENV_IS_IN_NAND |
| 135 | #define CONFIG_ENV_SIZE (64 * 2048) |
| 136 | #define CONFIG_ENV_RANGE (4 * 64 * 2048) |
| 137 | #define CONFIG_ENV_OFFSET (12 * 64 * 2048) |
| 138 | #endif |
| 139 | |
Sanchayan Maity | 7755e53 | 2015-04-17 18:56:42 +0530 | [diff] [blame] | 140 | /* USB Host Support */ |
Sanchayan Maity | 7755e53 | 2015-04-17 18:56:42 +0530 | [diff] [blame] | 141 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
| 142 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 143 | |
Sanchayan Maity | 7755e53 | 2015-04-17 18:56:42 +0530 | [diff] [blame] | 144 | /* USB DFU */ |
Marcel Ziswiler | 2e3b3d5 | 2019-03-25 17:25:02 +0100 | [diff] [blame^] | 145 | #define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) |
Sanchayan Maity | 7755e53 | 2015-04-17 18:56:42 +0530 | [diff] [blame] | 146 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 147 | #endif /* __CONFIG_H */ |