blob: 1ba4d22bdddc353da9ed28748e764ae4810f8e08 [file] [log] [blame]
Christophe Leroy684a4852017-07-06 10:33:11 +02001/*
2 * (C) Copyright 2000
3 * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <mpc8xx.h>
Christophe Leroy394f9b32017-07-06 10:33:13 +020010#include <asm/io.h>
Christophe Leroy684a4852017-07-06 10:33:11 +020011
12void mpc8xx_reginfo(void)
13{
Christophe Leroy394f9b32017-07-06 10:33:13 +020014 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
15 memctl8xx_t __iomem *memctl = &immap->im_memctl;
16 sysconf8xx_t __iomem *sysconf = &immap->im_siu_conf;
17 sit8xx_t __iomem *timers = &immap->im_sit;
Christophe Leroy684a4852017-07-06 10:33:11 +020018
19 /* Hopefully more PowerPC knowledgable people will add code to display
20 * other useful registers
21 */
22
Christophe Leroy48f896d2017-07-06 10:33:17 +020023 printf("\nSystem Configuration registers\n"
Christophe Leroy684a4852017-07-06 10:33:11 +020024 "\tIMMR\t0x%08X\n", get_immr(0));
25
Christophe Leroy394f9b32017-07-06 10:33:13 +020026 printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr));
27 printf("\tSYPCR\t0x%08X\n", in_be32(&sysconf->sc_sypcr));
Christophe Leroy684a4852017-07-06 10:33:11 +020028
Christophe Leroy394f9b32017-07-06 10:33:13 +020029 printf("\tSWT\t0x%08X", in_be32(&sysconf->sc_swt));
30 printf("\tSWSR\t0x%04X\n", in_be16(&sysconf->sc_swsr));
Christophe Leroy684a4852017-07-06 10:33:11 +020031
32 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
Christophe Leroy394f9b32017-07-06 10:33:13 +020033 in_be32(&sysconf->sc_sipend), in_be32(&sysconf->sc_simask));
Christophe Leroy684a4852017-07-06 10:33:11 +020034 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
Christophe Leroy394f9b32017-07-06 10:33:13 +020035 in_be32(&sysconf->sc_siel), in_be32(&sysconf->sc_sivec));
Christophe Leroy684a4852017-07-06 10:33:11 +020036 printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
Christophe Leroy394f9b32017-07-06 10:33:13 +020037 in_be32(&sysconf->sc_tesr), in_be32(&sysconf->sc_sdcr));
Christophe Leroy684a4852017-07-06 10:33:11 +020038
Christophe Leroy394f9b32017-07-06 10:33:13 +020039 printf("Memory Controller Registers\n");
40 printf("\tBR0\t0x%08X\tOR0\t0x%08X\n", in_be32(&memctl->memc_br0),
41 in_be32(&memctl->memc_or0));
42 printf("\tBR1\t0x%08X\tOR1\t0x%08X\n", in_be32(&memctl->memc_br1),
43 in_be32(&memctl->memc_or1));
44 printf("\tBR2\t0x%08X\tOR2\t0x%08X\n", in_be32(&memctl->memc_br2),
45 in_be32(&memctl->memc_or2));
46 printf("\tBR3\t0x%08X\tOR3\t0x%08X\n", in_be32(&memctl->memc_br3),
47 in_be32(&memctl->memc_or3));
48 printf("\tBR4\t0x%08X\tOR4\t0x%08X\n", in_be32(&memctl->memc_br4),
49 in_be32(&memctl->memc_or4));
50 printf("\tBR5\t0x%08X\tOR5\t0x%08X\n", in_be32(&memctl->memc_br5),
51 in_be32(&memctl->memc_or5));
52 printf("\tBR6\t0x%08X\tOR6\t0x%08X\n", in_be32(&memctl->memc_br6),
53 in_be32(&memctl->memc_or6));
54 printf("\tBR7\t0x%08X\tOR7\t0x%08X\n", in_be32(&memctl->memc_br7),
55 in_be32(&memctl->memc_or7));
56 printf("\n\tmamr\t0x%08X\tmbmr\t0x%08X\n", in_be32(&memctl->memc_mamr),
57 in_be32(&memctl->memc_mbmr));
58 printf("\tmstat\t0x%04X\tmptpr\t0x%04X\n", in_be16(&memctl->memc_mstat),
59 in_be16(&memctl->memc_mptpr));
60 printf("\tmdr\t0x%08X\n", in_be32(&memctl->memc_mdr));
Christophe Leroy684a4852017-07-06 10:33:11 +020061
Christophe Leroy394f9b32017-07-06 10:33:13 +020062 printf("\nSystem Integration Timers\n");
63 printf("\tTBSCR\t0x%04X\tRTCSC\t0x%04X\n",
64 in_be16(&timers->sit_tbscr), in_be16(&timers->sit_rtcsc));
65 printf("\tPISCR\t0x%04X\n", in_be16(&timers->sit_piscr));
Christophe Leroy684a4852017-07-06 10:33:11 +020066
67 /*
68 * May be some CPM info here?
69 */
70}