Blame - configs/puma-rk3399_defconfig - filogic/uboot

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Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	1	CONFIG_ARM=y
Tom Rini	e1e8544	2021-08-27 21:18:30 -0400	[diff] [blame]	2	CONFIG_SKIP_LOWLEVEL_INIT=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	3	CONFIG_ARCH_ROCKCHIP=y
Tom Rini	07edfae	2018-02-03 12:10:38 -0500	[diff] [blame]	4	CONFIG_SYS_TEXT_BASE=0x00200000
Simon Glass	035939e	2021-07-10 21:14:30 -0600	[diff] [blame]	5	CONFIG_SPL_GPIO=y
Tom Rini	2e262c4	2020-08-10 15:31:07 -0400	[diff] [blame]	6	CONFIG_NR_DRAM_BANKS=1
Tom Rini	f6e6e1a	2020-01-22 13:38:00 -0500	[diff] [blame]	7	CONFIG_ENV_OFFSET=0x3F8000
Tom Rini	a20e51f	2021-06-28 10:17:29 -0400	[diff] [blame]	8	CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou"
Tom Rini	0332a1a	2020-07-06 13:54:25 -0400	[diff] [blame]	9	CONFIG_SPL_TEXT_BASE=0xff8c2000
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	10	CONFIG_ROCKCHIP_RK3399=y
Philipp Tomsich	7427c39	2017-11-24 14:44:59 +0100	[diff] [blame]	11	CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
Tom Rini	79f4eea	2017-05-01 11:41:11 -0400	[diff] [blame]	12	CONFIG_TARGET_PUMA_RK3399=y
Tom Rini	e0056d7	2018-06-04 11:57:37 -0400	[diff] [blame]	13	CONFIG_DEBUG_UART_BASE=0xFF180000
				14	CONFIG_DEBUG_UART_CLOCK=24000000
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	15	CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glass	a582047	2021-08-08 12:20:14 -0600	[diff] [blame]	16	CONFIG_SPL_SPI=y
Tom Rini	0997ee0	2021-08-23 10:25:31 -0400	[diff] [blame]	17	CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini	4b2fcb3	2022-04-08 13:36:51 -0400	[diff] [blame]	18	CONFIG_DEBUG_UART=y
Klaus Goger	2b6b4f2	2018-05-25 23:45:05 +0200	[diff] [blame]	19	CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
Mario Six	f705544	2018-03-28 14:38:17 +0200	[diff] [blame]	20	CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Rini	f92b6fa	2020-10-09 12:22:06 -0400	[diff] [blame]	21	CONFIG_MISC_INIT_R=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	22	# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	23	CONFIG_SPL_STACK_R=y
				24	CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
				25	CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
Simon Glass	bccfc2e	2021-07-10 21:14:36 -0600	[diff] [blame]	26	CONFIG_SPL_I2C=y
Simon Glass	e91ac4c	2021-07-10 21:14:24 -0600	[diff] [blame]	27	CONFIG_SPL_POWER=y
Marek Vasut	e254225	2018-04-07 16:05:27 +0200	[diff] [blame]	28	CONFIG_SPL_SPI_LOAD=y
Tom Rini	e22fa4f	2021-08-10 15:08:46 -0400	[diff] [blame]	29	CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	30	CONFIG_CMD_BOOTZ=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	31	CONFIG_CMD_GPT=y
Tom Rini	78873cd	2017-08-14 19:58:53 -0400	[diff] [blame]	32	CONFIG_CMD_I2C=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	33	CONFIG_CMD_MMC=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	34	CONFIG_CMD_SPI=y
				35	CONFIG_CMD_USB=y
				36	# CONFIG_CMD_SETEXPR is not set
Philipp Tomsich	8e530f2	2017-06-06 09:15:15 +0200	[diff] [blame]	37	CONFIG_CMD_BMP=y
				38	CONFIG_CMD_CACHE=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	39	CONFIG_CMD_TIME=y
Philipp Tomsich	8e530f2	2017-06-06 09:15:15 +0200	[diff] [blame]	40	CONFIG_CMD_PMIC=y
				41	CONFIG_CMD_REGULATOR=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	42	CONFIG_SPL_OF_CONTROL=y
Philipp Tomsich	00fd83f	2017-09-12 17:32:29 +0200	[diff] [blame]	43	CONFIG_OF_LIVE=y
Philipp Tomsich	57806cb	2017-05-31 18:18:50 +0200	[diff] [blame]	44	CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Adam Ford	710966e	2020-07-03 06:48:56 -0500	[diff] [blame]	45	CONFIG_ENV_OVERWRITE=y
Tom Rini	5b0b040	2017-08-28 07:16:32 -0400	[diff] [blame]	46	CONFIG_ENV_IS_IN_MMC=y
Tom Rini	ca63e71	2019-11-12 22:46:36 -0500	[diff] [blame]	47	CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rini	eb1f909	2020-07-24 17:14:47 -0400	[diff] [blame]	48	CONFIG_SYS_MMC_ENV_DEV=1
Tom Rini	ae21e7f	2021-08-30 09:16:29 -0400	[diff] [blame]	49	CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
Hugh Cole-Baker	2d33823	2020-11-22 13:03:46 +0000	[diff] [blame]	50	CONFIG_SPL_DM_SEQ_ALIAS=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	51	CONFIG_ROCKCHIP_GPIO=y
Philipp Tomsich	a4dbfc3	2017-05-31 18:18:49 +0200	[diff] [blame]	52	CONFIG_SYS_I2C_ROCKCHIP=y
Philipp Tomsich	f781e80	2017-05-05 19:21:41 +0200	[diff] [blame]	53	CONFIG_MISC=y
				54	CONFIG_ROCKCHIP_EFUSE=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	55	CONFIG_MMC_DW=y
				56	CONFIG_MMC_DW_ROCKCHIP=y
				57	CONFIG_MMC_SDHCI=y
Philipp Tomsich	df23b0d	2018-03-26 19:59:08 +0200	[diff] [blame]	58	CONFIG_MMC_SDHCI_SDMA=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	59	CONFIG_MMC_SDHCI_ROCKCHIP=y
Hugh Cole-Baker	2d33823	2020-11-22 13:03:46 +0000	[diff] [blame]	60	CONFIG_SF_DEFAULT_BUS=1
Patrick Delaunay	0df8104	2019-02-27 15:20:36 +0100	[diff] [blame]	61	CONFIG_SF_DEFAULT_SPEED=20000000
Philipp Tomsich	b1c07ff	2019-02-03 15:59:23 +0100	[diff] [blame]	62	CONFIG_SPI_FLASH_GIGADEVICE=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	63	CONFIG_SPI_FLASH_WINBOND=y
				64	CONFIG_PHY_MICREL=y
Philipp Tomsich	8732115	2017-10-30 14:44:55 +0100	[diff] [blame]	65	CONFIG_PHY_MICREL_KSZ90X1=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	66	CONFIG_DM_ETH=y
				67	CONFIG_ETH_DESIGNWARE=y
				68	CONFIG_GMAC_ROCKCHIP=y
Heiko Stuebner	f9fb955	2020-06-05 12:06:43 +0200	[diff] [blame]	69	CONFIG_PHY_ROCKCHIP_INNO_USB2=y
				70	CONFIG_PHY_ROCKCHIP_TYPEC=y
Philipp Tomsich	3baf440	2018-11-30 20:00:09 +0100	[diff] [blame]	71	CONFIG_DM_PMIC_FAN53555=y
Philipp Tomsich	222464f	2017-05-31 18:18:46 +0200	[diff] [blame]	72	CONFIG_PMIC_RK8XX=y
Simon Glass	6343ffb	2021-08-08 12:20:25 -0600	[diff] [blame]	73	CONFIG_SPL_PMIC_RK8XX=y
Philipp Tomsich	070aba9	2017-09-29 19:28:03 +0200	[diff] [blame]	74	CONFIG_SPL_DM_REGULATOR=y
Christoph Muellner	8356c89	2019-01-02 15:09:17 +0100	[diff] [blame]	75	CONFIG_REGULATOR_PWM=y
Philipp Tomsich	070aba9	2017-09-29 19:28:03 +0200	[diff] [blame]	76	CONFIG_SPL_DM_REGULATOR_FIXED=y
				77	CONFIG_DM_REGULATOR_GPIO=y
Philipp Tomsich	222464f	2017-05-31 18:18:46 +0200	[diff] [blame]	78	CONFIG_REGULATOR_RK8XX=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	79	CONFIG_PWM_ROCKCHIP=y
Heiko Stuebner	f9fb955	2020-06-05 12:06:43 +0200	[diff] [blame]	80	CONFIG_DM_RESET=y
Klaus Goger	cda97be	2018-04-13 10:54:28 +0200	[diff] [blame]	81	CONFIG_DM_RTC=y
				82	CONFIG_RTC_ISL1208=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	83	CONFIG_DEBUG_UART_SHIFT=2
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	84	CONFIG_ROCKCHIP_SPI=y
				85	CONFIG_SYSRESET=y
				86	CONFIG_USB=y
				87	CONFIG_USB_XHCI_HCD=y
				88	CONFIG_USB_XHCI_DWC3=y
				89	CONFIG_USB_EHCI_HCD=y
				90	CONFIG_USB_EHCI_GENERIC=y
Heiko Stuebner	f9fb955	2020-06-05 12:06:43 +0200	[diff] [blame]	91	CONFIG_USB_DWC3=y
				92	CONFIG_USB_DWC3_GENERIC=y
Chris Packham	547cf41	2017-08-28 20:50:45 +1200	[diff] [blame]	93	CONFIG_USB_HOST_ETHER=y
Chris Packham	b110e11	2017-08-28 20:50:46 +1200	[diff] [blame]	94	CONFIG_USB_ETHER_ASIX=y
				95	CONFIG_USB_ETHER_ASIX88179=y
				96	CONFIG_USB_ETHER_MCS7830=y
				97	CONFIG_USB_ETHER_RTL8152=y
				98	CONFIG_USB_ETHER_SMSC95XX=y
Philipp Tomsich	8e530f2	2017-06-06 09:15:15 +0200	[diff] [blame]	99	CONFIG_DM_VIDEO=y
Anatolij Gustschin	dba3670	2020-02-04 22:43:06 +0100	[diff] [blame]	100	# CONFIG_VIDEO_BPP8 is not set
Philipp Tomsich	8e530f2	2017-06-06 09:15:15 +0200	[diff] [blame]	101	CONFIG_DISPLAY=y
				102	CONFIG_VIDEO_ROCKCHIP=y
				103	CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Patrick Delaunay	b1f1763	2020-09-28 11:30:16 +0200	[diff] [blame]	104	CONFIG_BMP_16BPP=y
				105	CONFIG_BMP_24BPP=y
				106	CONFIG_BMP_32BPP=y
Philipp Tomsich	23aec1d	2017-03-28 18:48:52 +0200	[diff] [blame]	107	CONFIG_ERRNO_STR=y