Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> |
| 4 | * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc> |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _CONFIG_CONTROLCENTERDC_H |
| 8 | #define _CONFIG_CONTROLCENTERDC_H |
| 9 | |
| 10 | /* |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 11 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed |
| 12 | * for DDR ECC byte filling in the SPL before loading the main |
| 13 | * U-Boot into it. |
| 14 | */ |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 15 | |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 16 | /* Environment in SPI NOR flash */ |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 17 | |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 18 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
| 19 | |
| 20 | /* PCIe support */ |
| 21 | #ifndef CONFIG_SPL_BUILD |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 22 | #define CONFIG_PCI_SCAN_SHOW |
| 23 | #endif |
| 24 | |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 25 | /* SPL */ |
| 26 | /* |
| 27 | * Select the boot device here |
| 28 | * |
| 29 | * Currently supported are: |
| 30 | * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash |
| 31 | * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) |
| 32 | */ |
| 33 | #define SPL_BOOT_SPI_NOR_FLASH 1 |
| 34 | #define SPL_BOOT_SDIO_MMC_CARD 2 |
| 35 | #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH |
| 36 | |
| 37 | /* Defines for SPL */ |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 38 | #define CONFIG_SPL_SIZE (160 << 10) |
| 39 | |
| 40 | #if defined(CONFIG_SECURED_MODE_IMAGE) |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 41 | #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614) |
| 42 | #else |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 43 | #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30) |
| 44 | #endif |
| 45 | |
| 46 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) |
| 47 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) |
| 48 | |
| 49 | #ifdef CONFIG_SPL_BUILD |
| 50 | #define CONFIG_SYS_MALLOC_SIMPLE |
| 51 | #endif |
| 52 | |
| 53 | #define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10)) |
| 54 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) |
| 55 | |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 56 | #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD |
| 57 | /* SPL related MMC defines */ |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 58 | #ifdef CONFIG_SPL_BUILD |
| 59 | #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ |
| 60 | #endif |
| 61 | #endif |
| 62 | |
| 63 | /* |
| 64 | * Environment Configuration |
| 65 | */ |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 66 | |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 67 | #define CONFIG_HOSTNAME "ccdc" |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 68 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 69 | |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 70 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 71 | "netdev=eth1\0" \ |
| 72 | "consoledev=ttyS1\0" \ |
| 73 | "u-boot=u-boot.bin\0" \ |
| 74 | "bootfile_addr=1000000\0" \ |
| 75 | "keyprogram_addr=3000000\0" \ |
| 76 | "keyprogram_file=keyprogram.img\0" \ |
| 77 | "fdtfile=controlcenterdc.dtb\0" \ |
| 78 | "load=tftpboot ${loadaddr} ${u-boot}\0" \ |
| 79 | "mmcdev=0:2\0" \ |
| 80 | "update=sf probe 1:0;" \ |
| 81 | " sf erase 0 +${filesize};" \ |
| 82 | " sf write ${fileaddr} 0 ${filesize}\0" \ |
| 83 | "upd=run load update\0" \ |
| 84 | "fdt_high=0x10000000\0" \ |
| 85 | "initrd_high=0x10000000\0" \ |
| 86 | "loadkeyprogram=tpm flush_keys;" \ |
| 87 | " mmc rescan;" \ |
| 88 | " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\ |
| 89 | " source ${keyprogram_addr}:script@1\0" \ |
| 90 | "gpio1=gpio@22_25\0" \ |
| 91 | "gpio2=A29\0" \ |
| 92 | "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \ |
| 93 | "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \ |
| 94 | "bootfail=for i in ${blinkseq}; do" \ |
| 95 | " if test $i -eq 0; then" \ |
| 96 | " gpio clear ${gpio1}; gpio set ${gpio2};" \ |
| 97 | " elif test $i -eq 1; then" \ |
| 98 | " gpio clear ${gpio1}; gpio clear ${gpio2};" \ |
| 99 | " elif test $i -eq 2; then" \ |
| 100 | " gpio set ${gpio1}; gpio set ${gpio2};" \ |
| 101 | " else;" \ |
| 102 | " gpio clear ${gpio1}; gpio set ${gpio2};" \ |
| 103 | " fi; sleep 0.12; done\0" |
| 104 | |
Dirk Eibach | fb60594 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 105 | /* |
| 106 | * mv-common.h should be defined after CMD configs since it used them |
| 107 | * to enable certain macros |
| 108 | */ |
| 109 | #include "mv-common.h" |
| 110 | |
| 111 | #endif /* _CONFIG_CONTROLCENTERDC_H */ |