Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 1 | /* |
| 2 | * board/renesas/ulcb/ulcb.c |
| 3 | * This file is ULCB board support. |
| 4 | * |
| 5 | * Copyright (C) 2017 Renesas Electronics Corporation |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #include <common.h> |
| 11 | #include <malloc.h> |
| 12 | #include <netdev.h> |
| 13 | #include <dm.h> |
| 14 | #include <dm/platform_data/serial_sh.h> |
| 15 | #include <asm/processor.h> |
| 16 | #include <asm/mach-types.h> |
| 17 | #include <asm/io.h> |
| 18 | #include <linux/errno.h> |
| 19 | #include <asm/arch/sys_proto.h> |
| 20 | #include <asm/gpio.h> |
| 21 | #include <asm/arch/gpio.h> |
| 22 | #include <asm/arch/rmobile.h> |
| 23 | #include <asm/arch/rcar-mstp.h> |
| 24 | #include <asm/arch/sh_sdhi.h> |
| 25 | #include <i2c.h> |
| 26 | #include <mmc.h> |
| 27 | |
| 28 | DECLARE_GLOBAL_DATA_PTR; |
| 29 | |
| 30 | #define CPGWPCR 0xE6150904 |
| 31 | #define CPGWPR 0xE615090C |
| 32 | |
| 33 | #define CLK2MHZ(clk) (clk / 1000 / 1000) |
| 34 | void s_init(void) |
| 35 | { |
| 36 | struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
| 37 | struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; |
| 38 | |
| 39 | /* Watchdog init */ |
| 40 | writel(0xA5A5A500, &rwdt->rwtcsra); |
| 41 | writel(0xA5A5A500, &swdt->swtcsra); |
| 42 | |
| 43 | writel(0xA5A50000, CPGWPCR); |
| 44 | writel(0xFFFFFFFF, CPGWPR); |
| 45 | } |
| 46 | |
| 47 | #define GSX_MSTP112 BIT(12) /* 3DG */ |
| 48 | #define TMU0_MSTP125 BIT(25) /* secure */ |
| 49 | #define TMU1_MSTP124 BIT(24) /* non-secure */ |
| 50 | #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ |
| 51 | #define ETHERAVB_MSTP812 BIT(12) |
| 52 | #define DVFS_MSTP926 BIT(26) |
| 53 | #define SD0_MSTP314 BIT(14) |
| 54 | #define SD1_MSTP313 BIT(13) |
| 55 | #define SD2_MSTP312 BIT(12) /* either MMC0 */ |
| 56 | |
| 57 | #define SD0CKCR 0xE6150074 |
| 58 | #define SD1CKCR 0xE6150078 |
| 59 | #define SD2CKCR 0xE6150268 |
| 60 | #define SD3CKCR 0xE615026C |
| 61 | |
| 62 | int board_early_init_f(void) |
| 63 | { |
| 64 | /* TMU0,1 */ /* which use ? */ |
| 65 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); |
| 66 | /* SCIF2 */ |
| 67 | mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310); |
| 68 | /* EHTERAVB */ |
| 69 | mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812); |
| 70 | /* eMMC */ |
| 71 | mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312); |
| 72 | /* SDHI0 */ |
| 73 | mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314); |
| 74 | |
| 75 | writel(0, SD0CKCR); |
| 76 | writel(0, SD1CKCR); |
| 77 | writel(0, SD2CKCR); |
| 78 | writel(0, SD3CKCR); |
| 79 | |
| 80 | #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) |
| 81 | /* DVFS for reset */ |
| 82 | mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); |
| 83 | #endif |
| 84 | return 0; |
| 85 | } |
| 86 | |
| 87 | /* SYSC */ |
| 88 | /* R/- 32 Power status register 2(3DG) */ |
| 89 | #define SYSC_PWRSR2 0xE6180100 |
| 90 | /* -/W 32 Power resume control register 2 (3DG) */ |
| 91 | #define SYSC_PWRONCR2 0xE618010C |
| 92 | |
| 93 | int board_init(void) |
| 94 | { |
| 95 | /* adress of boot parameters */ |
| 96 | gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; |
| 97 | |
| 98 | /* Init PFC controller */ |
| 99 | #if defined(CONFIG_R8A7795) |
| 100 | r8a7795_pinmux_init(); |
| 101 | #elif defined(CONFIG_R8A7796) |
| 102 | r8a7796_pinmux_init(); |
| 103 | #endif |
| 104 | |
| 105 | /* USB1 pull-up */ |
| 106 | setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); |
| 107 | |
Marek Vasut | 6b1bcd1 | 2017-08-28 14:12:34 +0200 | [diff] [blame] | 108 | #ifdef CONFIG_RENESAS_RAVB |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 109 | /* EtherAVB Enable */ |
| 110 | /* GPSR2 */ |
| 111 | gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL); |
| 112 | gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL); |
| 113 | gpio_request(GPIO_GFN_AVB_LINK, NULL); |
| 114 | gpio_request(GPIO_GFN_AVB_PHY_INT, NULL); |
| 115 | gpio_request(GPIO_GFN_AVB_MAGIC, NULL); |
| 116 | gpio_request(GPIO_GFN_AVB_MDC, NULL); |
| 117 | |
| 118 | /* IPSR0 */ |
| 119 | gpio_request(GPIO_IFN_AVB_MDC, NULL); |
| 120 | gpio_request(GPIO_IFN_AVB_MAGIC, NULL); |
| 121 | gpio_request(GPIO_IFN_AVB_PHY_INT, NULL); |
| 122 | gpio_request(GPIO_IFN_AVB_LINK, NULL); |
| 123 | gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL); |
| 124 | gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL); |
| 125 | /* IPSR1 */ |
| 126 | gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL); |
| 127 | /* IPSR2 */ |
| 128 | gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL); |
| 129 | /* IPSR3 */ |
| 130 | gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL); |
| 131 | |
| 132 | /* AVB_PHY_RST */ |
| 133 | gpio_request(GPIO_GP_2_10, NULL); |
| 134 | gpio_direction_output(GPIO_GP_2_10, 0); |
| 135 | mdelay(20); |
| 136 | gpio_set_value(GPIO_GP_2_10, 1); |
| 137 | udelay(1); |
| 138 | #endif |
| 139 | |
Marek Vasut | 22eb59d | 2017-08-28 14:12:54 +0200 | [diff] [blame] | 140 | #ifdef CONFIG_MMC |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 141 | /* SDHI0 */ |
| 142 | gpio_request(GPIO_GFN_SD0_DAT0, NULL); |
| 143 | gpio_request(GPIO_GFN_SD0_DAT1, NULL); |
| 144 | gpio_request(GPIO_GFN_SD0_DAT2, NULL); |
| 145 | gpio_request(GPIO_GFN_SD0_DAT3, NULL); |
| 146 | gpio_request(GPIO_GFN_SD0_CLK, NULL); |
| 147 | gpio_request(GPIO_GFN_SD0_CMD, NULL); |
| 148 | gpio_request(GPIO_GFN_SD0_CD, NULL); |
| 149 | gpio_request(GPIO_GFN_SD0_WP, NULL); |
| 150 | |
| 151 | gpio_request(GPIO_GP_5_2, NULL); |
| 152 | gpio_request(GPIO_GP_5_1, NULL); |
| 153 | gpio_direction_output(GPIO_GP_5_2, 1); /* power on */ |
| 154 | gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */ |
| 155 | |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 156 | /* SDHI1/SDHI2 eMMC */ |
| 157 | gpio_request(GPIO_GFN_SD1_DAT0, NULL); |
| 158 | gpio_request(GPIO_GFN_SD1_DAT1, NULL); |
| 159 | gpio_request(GPIO_GFN_SD1_DAT2, NULL); |
| 160 | gpio_request(GPIO_GFN_SD1_DAT3, NULL); |
| 161 | gpio_request(GPIO_GFN_SD2_DAT0, NULL); |
| 162 | gpio_request(GPIO_GFN_SD2_DAT1, NULL); |
| 163 | gpio_request(GPIO_GFN_SD2_DAT2, NULL); |
| 164 | gpio_request(GPIO_GFN_SD2_DAT3, NULL); |
| 165 | gpio_request(GPIO_GFN_SD2_CLK, NULL); |
| 166 | #if defined(CONFIG_R8A7795) |
| 167 | gpio_request(GPIO_GFN_SD2_CMD, NULL); |
| 168 | #elif defined(CONFIG_R8A7796) |
| 169 | gpio_request(GPIO_FN_SD2_CMD, NULL); |
| 170 | #else |
| 171 | #error Only R8A7795 and R87796 is supported |
| 172 | #endif |
| 173 | gpio_request(GPIO_GP_5_3, NULL); |
| 174 | gpio_request(GPIO_GP_5_9, NULL); |
| 175 | gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */ |
| 176 | gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */ |
Marek Vasut | 22eb59d | 2017-08-28 14:12:54 +0200 | [diff] [blame] | 177 | #endif |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 178 | |
Marek Vasut | 7cf1c7f | 2017-08-20 17:13:48 +0200 | [diff] [blame] | 179 | return 0; |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 180 | } |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 181 | |
| 182 | int dram_init(void) |
| 183 | { |
| 184 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
| 185 | #if (CONFIG_NR_DRAM_BANKS >= 2) |
| 186 | gd->ram_size += PHYS_SDRAM_2_SIZE; |
| 187 | #endif |
| 188 | #if (CONFIG_NR_DRAM_BANKS >= 3) |
| 189 | gd->ram_size += PHYS_SDRAM_3_SIZE; |
| 190 | #endif |
| 191 | #if (CONFIG_NR_DRAM_BANKS >= 4) |
| 192 | gd->ram_size += PHYS_SDRAM_4_SIZE; |
| 193 | #endif |
| 194 | |
| 195 | return 0; |
| 196 | } |
| 197 | |
| 198 | int dram_init_banksize(void) |
| 199 | { |
| 200 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 201 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
| 202 | #if (CONFIG_NR_DRAM_BANKS >= 2) |
| 203 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
| 204 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
| 205 | #endif |
| 206 | #if (CONFIG_NR_DRAM_BANKS >= 3) |
| 207 | gd->bd->bi_dram[2].start = PHYS_SDRAM_3; |
| 208 | gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; |
| 209 | #endif |
| 210 | #if (CONFIG_NR_DRAM_BANKS >= 4) |
| 211 | gd->bd->bi_dram[3].start = PHYS_SDRAM_4; |
| 212 | gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; |
| 213 | #endif |
| 214 | return 0; |
| 215 | } |
| 216 | |
| 217 | const struct rmobile_sysinfo sysinfo = { |
| 218 | CONFIG_RCAR_BOARD_STRING |
| 219 | }; |