| Stefan Roese | a6f2ea4 | 2020-06-30 12:08:58 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2019-2020 |
| 4 | * Marvell <www.marvell.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __OCTEON_COMMON_H__ |
| 8 | #define __OCTEON_COMMON_H__ |
| 9 | |
| Stefan Roese | 82ba278 | 2020-09-02 08:29:10 +0200 | [diff] [blame] | 10 | #if defined(CONFIG_RAM_OCTEON) |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 11 | #define CFG_SYS_INIT_SP_OFFSET 0x20180000 |
| Stefan Roese | 82ba278 | 2020-09-02 08:29:10 +0200 | [diff] [blame] | 12 | #else |
| 13 | /* No DDR init -> run in L2 cache with limited resources */ |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 14 | #define CFG_SYS_INIT_SP_OFFSET 0x00180000 |
| Stefan Roese | 82ba278 | 2020-09-02 08:29:10 +0200 | [diff] [blame] | 15 | #endif |
| 16 | |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 17 | #define CFG_SYS_SDRAM_BASE 0xffffffff80000000 |
| Stefan Roese | a6f2ea4 | 2020-06-30 12:08:58 +0200 | [diff] [blame] | 18 | |
| Stefan Roese | a6f2ea4 | 2020-06-30 12:08:58 +0200 | [diff] [blame] | 19 | #endif /* __OCTEON_COMMON_H__ */ |