Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2021 Gateworks Corporation |
| 4 | */ |
| 5 | |
| 6 | #ifndef __IMX8MM_VENICE_H |
| 7 | #define __IMX8MM_VENICE_H |
| 8 | |
| 9 | #include <asm/arch/imx-regs.h> |
| 10 | #include <linux/sizes.h> |
| 11 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 12 | #define CFG_SYS_UBOOT_BASE \ |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 13 | (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) |
| 14 | |
| 15 | #ifdef CONFIG_SPL_BUILD |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 16 | /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ |
Tom Rini | fb52b94 | 2022-12-04 10:04:49 -0500 | [diff] [blame] | 17 | #define CFG_MALLOC_F_ADDR 0x930000 |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 18 | #endif |
| 19 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 20 | /* Enable Distro Boot */ |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 21 | #define BOOT_TARGET_DEVICES(func) \ |
| 22 | func(MMC, mmc, 1) \ |
| 23 | func(MMC, mmc, 2) \ |
Tim Harvey | e9302ec | 2022-04-13 08:42:52 -0700 | [diff] [blame] | 24 | func(USB, usb, 0) \ |
| 25 | func(USB, usb, 1) \ |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 26 | func(DHCP, dhcp, na) |
| 27 | #include <config_distro_bootcmd.h> |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 28 | #define CFG_EXTRA_ENV_SETTINGS \ |
Tim Harvey | 942bf43 | 2022-11-04 08:51:45 -0700 | [diff] [blame] | 29 | BOOTENV |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 30 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 31 | #define CFG_SYS_INIT_RAM_ADDR 0x40000000 |
| 32 | #define CFG_SYS_INIT_RAM_SIZE SZ_2M |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 33 | |
Tim Harvey | 5547529 | 2023-06-23 09:44:17 -0700 | [diff] [blame] | 34 | /* SDRAM configuration: 4GiB */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 35 | #define CFG_SYS_SDRAM_BASE 0x40000000 |
Tim Harvey | 5547529 | 2023-06-23 09:44:17 -0700 | [diff] [blame] | 36 | #define PHYS_SDRAM 0x40000000 |
| 37 | #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */ |
| 38 | #define PHYS_SDRAM_2 0xC0000000 |
| 39 | #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 40 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 41 | #endif |