Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 2 | /* |
| 3 | * PCIe driver for Marvell MVEBU SoCs |
| 4 | * |
| 5 | * Based on Barebox drivers/pci/pci-mvebu.c |
| 6 | * |
| 7 | * Ported to U-Boot by: |
| 8 | * Anton Schubert <anton.schubert@gmx.de> |
| 9 | * Stefan Roese <sr@denx.de> |
Pali Rohár | 028ac88 | 2021-12-16 12:04:06 +0100 | [diff] [blame] | 10 | * Pali Rohár <pali@kernel.org> |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #include <common.h> |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 14 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 15 | #include <log.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 16 | #include <malloc.h> |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 17 | #include <dm/device-internal.h> |
| 18 | #include <dm/lists.h> |
| 19 | #include <dm/of_access.h> |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 20 | #include <pci.h> |
Pali Rohár | 5fc93e2 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 21 | #include <reset.h> |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 22 | #include <asm/io.h> |
| 23 | #include <asm/arch/cpu.h> |
| 24 | #include <asm/arch/soc.h> |
Pali Rohár | 62297ec | 2022-08-05 16:03:41 +0200 | [diff] [blame] | 25 | #include <asm/gpio.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 26 | #include <linux/bitops.h> |
Pali Rohár | 91d02fb | 2021-12-21 12:20:17 +0100 | [diff] [blame] | 27 | #include <linux/delay.h> |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 28 | #include <linux/errno.h> |
| 29 | #include <linux/ioport.h> |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 30 | #include <linux/mbus.h> |
Simon Glass | bdd5f81 | 2023-09-14 18:21:46 -0600 | [diff] [blame^] | 31 | #include <linux/printk.h> |
Pali Rohár | ca69af4 | 2021-12-21 12:20:13 +0100 | [diff] [blame] | 32 | #include <linux/sizes.h> |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 33 | |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 34 | /* PCIe unit register offsets */ |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 35 | #define MVPCIE_ROOT_PORT_PCI_CFG_OFF 0x0000 |
| 36 | #define MVPCIE_ROOT_PORT_PCI_EXP_OFF 0x0060 |
| 37 | #define MVPCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) |
| 38 | #define MVPCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) |
| 39 | #define MVPCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) |
| 40 | #define MVPCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) |
| 41 | #define MVPCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) |
| 42 | #define MVPCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) |
| 43 | #define MVPCIE_WIN5_CTRL_OFF 0x1880 |
| 44 | #define MVPCIE_WIN5_BASE_OFF 0x1884 |
| 45 | #define MVPCIE_WIN5_REMAP_OFF 0x188c |
| 46 | #define MVPCIE_CONF_ADDR_OFF 0x18f8 |
| 47 | #define MVPCIE_CONF_DATA_OFF 0x18fc |
| 48 | #define MVPCIE_CTRL_OFF 0x1a00 |
| 49 | #define MVPCIE_CTRL_RC_MODE BIT(1) |
| 50 | #define MVPCIE_STAT_OFF 0x1a04 |
| 51 | #define MVPCIE_STAT_BUS (0xff << 8) |
| 52 | #define MVPCIE_STAT_DEV (0x1f << 16) |
| 53 | #define MVPCIE_STAT_LINK_DOWN BIT(0) |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 54 | |
Pali Rohár | 91d02fb | 2021-12-21 12:20:17 +0100 | [diff] [blame] | 55 | #define LINK_WAIT_RETRIES 100 |
| 56 | #define LINK_WAIT_TIMEOUT 1000 |
| 57 | |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 58 | struct mvebu_pcie { |
| 59 | struct pci_controller hose; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 60 | void __iomem *base; |
| 61 | void __iomem *membase; |
| 62 | struct resource mem; |
| 63 | void __iomem *iobase; |
Phil Sutter | 09577aa | 2021-01-03 23:06:46 +0100 | [diff] [blame] | 64 | struct resource io; |
Pali Rohár | 62297ec | 2022-08-05 16:03:41 +0200 | [diff] [blame] | 65 | struct gpio_desc reset_gpio; |
Pali Rohár | bb26c4a | 2021-12-21 12:20:15 +0100 | [diff] [blame] | 66 | u32 intregs; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 67 | u32 port; |
| 68 | u32 lane; |
Pali Rohár | 5fc93e2 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 69 | bool is_x4; |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 70 | int devfn; |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 71 | int sec_busno; |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 72 | char name[16]; |
| 73 | unsigned int mem_target; |
| 74 | unsigned int mem_attr; |
Phil Sutter | 09577aa | 2021-01-03 23:06:46 +0100 | [diff] [blame] | 75 | unsigned int io_target; |
| 76 | unsigned int io_attr; |
Pali Rohár | 3166722 | 2021-11-11 16:35:45 +0100 | [diff] [blame] | 77 | u32 cfgcache[(0x3c - 0x10) / 4]; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 78 | }; |
| 79 | |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 80 | static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) |
| 81 | { |
| 82 | u32 val; |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 83 | val = readl(pcie->base + MVPCIE_STAT_OFF); |
| 84 | return !(val & MVPCIE_STAT_LINK_DOWN); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 85 | } |
| 86 | |
Pali Rohár | 91d02fb | 2021-12-21 12:20:17 +0100 | [diff] [blame] | 87 | static void mvebu_pcie_wait_for_link(struct mvebu_pcie *pcie) |
| 88 | { |
| 89 | int retries; |
| 90 | |
| 91 | /* check if the link is up or not */ |
| 92 | for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) { |
| 93 | if (mvebu_pcie_link_up(pcie)) { |
| 94 | printf("%s: Link up\n", pcie->name); |
| 95 | return; |
| 96 | } |
| 97 | |
| 98 | udelay(LINK_WAIT_TIMEOUT); |
| 99 | } |
| 100 | |
| 101 | printf("%s: Link down\n", pcie->name); |
| 102 | } |
| 103 | |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 104 | static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno) |
| 105 | { |
| 106 | u32 stat; |
| 107 | |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 108 | stat = readl(pcie->base + MVPCIE_STAT_OFF); |
| 109 | stat &= ~MVPCIE_STAT_BUS; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 110 | stat |= busno << 8; |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 111 | writel(stat, pcie->base + MVPCIE_STAT_OFF); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 112 | } |
| 113 | |
| 114 | static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno) |
| 115 | { |
| 116 | u32 stat; |
| 117 | |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 118 | stat = readl(pcie->base + MVPCIE_STAT_OFF); |
| 119 | stat &= ~MVPCIE_STAT_DEV; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 120 | stat |= devno << 16; |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 121 | writel(stat, pcie->base + MVPCIE_STAT_OFF); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 122 | } |
| 123 | |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 124 | static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose) |
| 125 | { |
| 126 | return container_of(hose, struct mvebu_pcie, hose); |
| 127 | } |
| 128 | |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 129 | static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie, |
| 130 | int busno, int dev, int func) |
Marek Behún | 8903673 | 2021-02-08 23:01:40 +0100 | [diff] [blame] | 131 | { |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 132 | /* On the root bus is only one PCI Bridge */ |
| 133 | if (busno == 0 && (dev != 0 || func != 0)) |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 134 | return false; |
Marek Behún | 8903673 | 2021-02-08 23:01:40 +0100 | [diff] [blame] | 135 | |
Pali Rohár | 2f9b519 | 2021-10-22 16:22:12 +0200 | [diff] [blame] | 136 | /* Access to other buses is possible when link is up */ |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 137 | if (busno != 0 && !mvebu_pcie_link_up(pcie)) |
Pali Rohár | 2f9b519 | 2021-10-22 16:22:12 +0200 | [diff] [blame] | 138 | return false; |
| 139 | |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 140 | /* On secondary bus can be only one PCIe device */ |
| 141 | if (busno == pcie->sec_busno && dev != 0) |
| 142 | return false; |
| 143 | |
| 144 | return true; |
Marek Behún | 8903673 | 2021-02-08 23:01:40 +0100 | [diff] [blame] | 145 | } |
| 146 | |
Simon Glass | 2a311e8 | 2020-01-27 08:49:37 -0700 | [diff] [blame] | 147 | static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 148 | uint offset, ulong *valuep, |
| 149 | enum pci_size_t size) |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 150 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 151 | struct mvebu_pcie *pcie = dev_get_plat(bus); |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 152 | int busno = PCI_BUS(bdf) - dev_seq(bus); |
| 153 | u32 addr, data; |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 154 | |
Marek Behún | 8903673 | 2021-02-08 23:01:40 +0100 | [diff] [blame] | 155 | debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", |
| 156 | PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 157 | |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 158 | if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) { |
Stefan Roese | 8d77b0a | 2021-01-25 15:25:31 +0100 | [diff] [blame] | 159 | debug("- out of range\n"); |
| 160 | *valuep = pci_get_ff(size); |
| 161 | return 0; |
| 162 | } |
| 163 | |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 164 | /* |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 165 | * The configuration space of the PCI Bridge on the root bus (zero) is |
Pali Rohár | 3166722 | 2021-11-11 16:35:45 +0100 | [diff] [blame] | 166 | * of Type 0 but the BAR registers (including ROM BAR) don't have the |
| 167 | * same meaning as in the PCIe specification. Therefore do not access |
| 168 | * BAR registers and non-common registers (those which have different |
| 169 | * meaning for Type 0 and Type 1 config space) of the PCI Bridge and |
| 170 | * instead read their content from driver virtual cfgcache[]. |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 171 | */ |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 172 | if (busno == 0 && ((offset >= 0x10 && offset < 0x34) || |
| 173 | (offset >= 0x38 && offset < 0x3c))) { |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 174 | data = pcie->cfgcache[(offset - 0x10) / 4]; |
| 175 | debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n", |
| 176 | offset, size, data); |
| 177 | *valuep = pci_conv_32_to_size(data, offset, size); |
| 178 | return 0; |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | /* |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 182 | * PCI bridge is device 0 at the root bus (zero) but mvebu has it |
| 183 | * mapped on secondary bus with device number 1. |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 184 | */ |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 185 | if (busno == 0) |
Pali Rohár | 43a9fc7 | 2021-11-26 11:42:45 +0100 | [diff] [blame] | 186 | addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset); |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 187 | else |
Pali Rohár | 43a9fc7 | 2021-11-26 11:42:45 +0100 | [diff] [blame] | 188 | addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 189 | |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 190 | /* write address */ |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 191 | writel(addr, pcie->base + MVPCIE_CONF_ADDR_OFF); |
Marek Behún | 9df558d | 2021-02-08 23:01:38 +0100 | [diff] [blame] | 192 | |
| 193 | /* read data */ |
Pali Rohár | 8922013 | 2021-10-22 16:22:09 +0200 | [diff] [blame] | 194 | switch (size) { |
| 195 | case PCI_SIZE_8: |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 196 | data = readb(pcie->base + MVPCIE_CONF_DATA_OFF + (offset & 3)); |
Pali Rohár | 8922013 | 2021-10-22 16:22:09 +0200 | [diff] [blame] | 197 | break; |
| 198 | case PCI_SIZE_16: |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 199 | data = readw(pcie->base + MVPCIE_CONF_DATA_OFF + (offset & 2)); |
Pali Rohár | 8922013 | 2021-10-22 16:22:09 +0200 | [diff] [blame] | 200 | break; |
| 201 | case PCI_SIZE_32: |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 202 | data = readl(pcie->base + MVPCIE_CONF_DATA_OFF); |
Pali Rohár | 8922013 | 2021-10-22 16:22:09 +0200 | [diff] [blame] | 203 | break; |
| 204 | default: |
| 205 | return -EINVAL; |
| 206 | } |
| 207 | |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 208 | if (busno == 0 && (offset & ~3) == (PCI_HEADER_TYPE & ~3)) { |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 209 | /* |
| 210 | * Change Header Type of PCI Bridge device to Type 1 |
| 211 | * (0x01, used by PCI Bridges) because mvebu reports |
| 212 | * Type 0 (0x00, used by Upstream and Endpoint devices). |
| 213 | */ |
| 214 | data = pci_conv_size_to_32(data, 0, offset, size); |
| 215 | data &= ~0x007f0000; |
| 216 | data |= PCI_HEADER_TYPE_BRIDGE << 16; |
| 217 | data = pci_conv_32_to_size(data, offset, size); |
| 218 | } |
| 219 | |
Marek Behún | d2ed1e5 | 2021-02-08 23:01:39 +0100 | [diff] [blame] | 220 | debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data); |
Pali Rohár | 8922013 | 2021-10-22 16:22:09 +0200 | [diff] [blame] | 221 | *valuep = data; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 226 | static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, |
| 227 | uint offset, ulong value, |
| 228 | enum pci_size_t size) |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 229 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 230 | struct mvebu_pcie *pcie = dev_get_plat(bus); |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 231 | int busno = PCI_BUS(bdf) - dev_seq(bus); |
| 232 | u32 addr, data; |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 233 | |
Marek Behún | 8903673 | 2021-02-08 23:01:40 +0100 | [diff] [blame] | 234 | debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", |
| 235 | PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); |
Marek Behún | d2ed1e5 | 2021-02-08 23:01:39 +0100 | [diff] [blame] | 236 | debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 237 | |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 238 | if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) { |
Stefan Roese | 8d77b0a | 2021-01-25 15:25:31 +0100 | [diff] [blame] | 239 | debug("- out of range\n"); |
| 240 | return 0; |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 241 | } |
| 242 | |
| 243 | /* |
Pali Rohár | 3166722 | 2021-11-11 16:35:45 +0100 | [diff] [blame] | 244 | * As explained in mvebu_pcie_read_config(), PCI Bridge Type 1 specific |
| 245 | * config registers are not available, so we write their content only |
| 246 | * into driver virtual cfgcache[]. |
| 247 | * And as explained in mvebu_pcie_probe(), mvebu has its own specific |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 248 | * way for configuring secondary bus number. |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 249 | */ |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 250 | if (busno == 0 && ((offset >= 0x10 && offset < 0x34) || |
| 251 | (offset >= 0x38 && offset < 0x3c))) { |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 252 | debug("Writing to cfgcache only\n"); |
| 253 | data = pcie->cfgcache[(offset - 0x10) / 4]; |
| 254 | data = pci_conv_size_to_32(data, value, offset, size); |
| 255 | /* mvebu PCI bridge does not have configurable bars */ |
| 256 | if ((offset & ~3) == PCI_BASE_ADDRESS_0 || |
Pali Rohár | 3166722 | 2021-11-11 16:35:45 +0100 | [diff] [blame] | 257 | (offset & ~3) == PCI_BASE_ADDRESS_1 || |
| 258 | (offset & ~3) == PCI_ROM_ADDRESS1) |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 259 | data = 0x0; |
| 260 | pcie->cfgcache[(offset - 0x10) / 4] = data; |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 261 | /* mvebu has its own way how to set PCI secondary bus number */ |
| 262 | if (offset == PCI_SECONDARY_BUS || |
| 263 | (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) { |
| 264 | pcie->sec_busno = (data >> 8) & 0xff; |
| 265 | mvebu_pcie_set_local_bus_nr(pcie, pcie->sec_busno); |
| 266 | debug("Secondary bus number was changed to %d\n", |
| 267 | pcie->sec_busno); |
| 268 | } |
| 269 | return 0; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 270 | } |
| 271 | |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 272 | /* |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 273 | * PCI bridge is device 0 at the root bus (zero) but mvebu has it |
| 274 | * mapped on secondary bus with device number 1. |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 275 | */ |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 276 | if (busno == 0) |
Pali Rohár | 43a9fc7 | 2021-11-26 11:42:45 +0100 | [diff] [blame] | 277 | addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset); |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 278 | else |
Pali Rohár | 43a9fc7 | 2021-11-26 11:42:45 +0100 | [diff] [blame] | 279 | addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 280 | |
Marek Behún | 9df558d | 2021-02-08 23:01:38 +0100 | [diff] [blame] | 281 | /* write address */ |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 282 | writel(addr, pcie->base + MVPCIE_CONF_ADDR_OFF); |
Marek Behún | 9df558d | 2021-02-08 23:01:38 +0100 | [diff] [blame] | 283 | |
| 284 | /* write data */ |
Pali Rohár | 35bce49 | 2021-10-22 16:22:08 +0200 | [diff] [blame] | 285 | switch (size) { |
| 286 | case PCI_SIZE_8: |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 287 | writeb(value, pcie->base + MVPCIE_CONF_DATA_OFF + (offset & 3)); |
Pali Rohár | 35bce49 | 2021-10-22 16:22:08 +0200 | [diff] [blame] | 288 | break; |
| 289 | case PCI_SIZE_16: |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 290 | writew(value, pcie->base + MVPCIE_CONF_DATA_OFF + (offset & 2)); |
Pali Rohár | 35bce49 | 2021-10-22 16:22:08 +0200 | [diff] [blame] | 291 | break; |
| 292 | case PCI_SIZE_32: |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 293 | writel(value, pcie->base + MVPCIE_CONF_DATA_OFF); |
Pali Rohár | 35bce49 | 2021-10-22 16:22:08 +0200 | [diff] [blame] | 294 | break; |
| 295 | default: |
| 296 | return -EINVAL; |
| 297 | } |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 298 | |
| 299 | return 0; |
| 300 | } |
| 301 | |
| 302 | /* |
| 303 | * Setup PCIE BARs and Address Decode Wins: |
Pali Rohár | 495f313 | 2021-11-11 16:35:42 +0100 | [diff] [blame] | 304 | * BAR[0] -> internal registers |
| 305 | * BAR[1] -> covers all DRAM banks |
| 306 | * BAR[2] -> disabled |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 307 | * WIN[0-3] -> DRAM bank[0-3] |
| 308 | */ |
| 309 | static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie) |
| 310 | { |
| 311 | const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info(); |
| 312 | u32 size; |
| 313 | int i; |
| 314 | |
| 315 | /* First, disable and clear BARs and windows. */ |
| 316 | for (i = 1; i < 3; i++) { |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 317 | writel(0, pcie->base + MVPCIE_BAR_CTRL_OFF(i)); |
| 318 | writel(0, pcie->base + MVPCIE_BAR_LO_OFF(i)); |
| 319 | writel(0, pcie->base + MVPCIE_BAR_HI_OFF(i)); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 320 | } |
| 321 | |
| 322 | for (i = 0; i < 5; i++) { |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 323 | writel(0, pcie->base + MVPCIE_WIN04_CTRL_OFF(i)); |
| 324 | writel(0, pcie->base + MVPCIE_WIN04_BASE_OFF(i)); |
| 325 | writel(0, pcie->base + MVPCIE_WIN04_REMAP_OFF(i)); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 326 | } |
| 327 | |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 328 | writel(0, pcie->base + MVPCIE_WIN5_CTRL_OFF); |
| 329 | writel(0, pcie->base + MVPCIE_WIN5_BASE_OFF); |
| 330 | writel(0, pcie->base + MVPCIE_WIN5_REMAP_OFF); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 331 | |
| 332 | /* Setup windows for DDR banks. Count total DDR size on the fly. */ |
| 333 | size = 0; |
| 334 | for (i = 0; i < dram->num_cs; i++) { |
| 335 | const struct mbus_dram_window *cs = dram->cs + i; |
| 336 | |
| 337 | writel(cs->base & 0xffff0000, |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 338 | pcie->base + MVPCIE_WIN04_BASE_OFF(i)); |
| 339 | writel(0, pcie->base + MVPCIE_WIN04_REMAP_OFF(i)); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 340 | writel(((cs->size - 1) & 0xffff0000) | |
| 341 | (cs->mbus_attr << 8) | |
| 342 | (dram->mbus_dram_target_id << 4) | 1, |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 343 | pcie->base + MVPCIE_WIN04_CTRL_OFF(i)); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 344 | |
| 345 | size += cs->size; |
| 346 | } |
| 347 | |
| 348 | /* Round up 'size' to the nearest power of two. */ |
| 349 | if ((size & (size - 1)) != 0) |
| 350 | size = 1 << fls(size); |
| 351 | |
| 352 | /* Setup BAR[1] to all DRAM banks. */ |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 353 | writel(dram->cs[0].base | 0xc, pcie->base + MVPCIE_BAR_LO_OFF(1)); |
| 354 | writel(0, pcie->base + MVPCIE_BAR_HI_OFF(1)); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 355 | writel(((size - 1) & 0xffff0000) | 0x1, |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 356 | pcie->base + MVPCIE_BAR_CTRL_OFF(1)); |
Pali Rohár | 495f313 | 2021-11-11 16:35:42 +0100 | [diff] [blame] | 357 | |
| 358 | /* Setup BAR[0] to internal registers. */ |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 359 | writel(pcie->intregs, pcie->base + MVPCIE_BAR_LO_OFF(0)); |
| 360 | writel(0, pcie->base + MVPCIE_BAR_HI_OFF(0)); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 361 | } |
| 362 | |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 363 | /* Only enable PCIe link, do not setup it */ |
| 364 | static int mvebu_pcie_enable_link(struct mvebu_pcie *pcie, ofnode node) |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 365 | { |
Pali Rohár | 5fc93e2 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 366 | struct reset_ctl rst; |
| 367 | int ret; |
| 368 | |
| 369 | ret = reset_get_by_index_nodev(node, 0, &rst); |
| 370 | if (ret == -ENOENT) { |
| 371 | return 0; |
| 372 | } else if (ret < 0) { |
| 373 | printf("%s: cannot get reset controller: %d\n", pcie->name, ret); |
| 374 | return ret; |
| 375 | } |
| 376 | |
| 377 | ret = reset_request(&rst); |
| 378 | if (ret) { |
| 379 | printf("%s: cannot request reset controller: %d\n", pcie->name, ret); |
| 380 | return ret; |
| 381 | } |
| 382 | |
| 383 | ret = reset_deassert(&rst); |
| 384 | reset_free(&rst); |
| 385 | if (ret) { |
| 386 | printf("%s: cannot enable PCIe port: %d\n", pcie->name, ret); |
| 387 | return ret; |
| 388 | } |
| 389 | |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 390 | return 0; |
| 391 | } |
| 392 | |
| 393 | /* Setup PCIe link but do not enable it */ |
| 394 | static void mvebu_pcie_setup_link(struct mvebu_pcie *pcie) |
| 395 | { |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 396 | u32 reg; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 397 | |
Pali Rohár | 6f3e57a | 2021-10-22 16:22:14 +0200 | [diff] [blame] | 398 | /* Setup PCIe controller to Root Complex mode */ |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 399 | reg = readl(pcie->base + MVPCIE_CTRL_OFF); |
| 400 | reg |= MVPCIE_CTRL_RC_MODE; |
| 401 | writel(reg, pcie->base + MVPCIE_CTRL_OFF); |
Pali Rohár | 5fc93e2 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 402 | |
| 403 | /* |
| 404 | * Set Maximum Link Width to X1 or X4 in Root Port's PCIe Link |
| 405 | * Capability register. This register is defined by PCIe specification |
| 406 | * as read-only but this mvebu controller has it as read-write and must |
| 407 | * be set to number of SerDes PCIe lanes (1 or 4). If this register is |
| 408 | * not set correctly then link with endpoint card is not established. |
| 409 | */ |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 410 | reg = readl(pcie->base + MVPCIE_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_LNKCAP); |
Pali Rohár | 5fc93e2 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 411 | reg &= ~PCI_EXP_LNKCAP_MLW; |
| 412 | reg |= (pcie->is_x4 ? 4 : 1) << 4; |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 413 | writel(reg, pcie->base + MVPCIE_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_LNKCAP); |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 414 | } |
| 415 | |
| 416 | static int mvebu_pcie_probe(struct udevice *dev) |
| 417 | { |
| 418 | struct mvebu_pcie *pcie = dev_get_plat(dev); |
| 419 | struct udevice *ctlr = pci_get_controller(dev); |
| 420 | struct pci_controller *hose = dev_get_uclass_priv(ctlr); |
| 421 | u32 reg; |
Pali Rohár | 62297ec | 2022-08-05 16:03:41 +0200 | [diff] [blame] | 422 | int ret; |
| 423 | |
| 424 | /* Request for optional PERST# GPIO */ |
| 425 | ret = gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio, GPIOD_IS_OUT); |
| 426 | if (ret && ret != -ENOENT) { |
| 427 | printf("%s: unable to request reset-gpios: %d\n", pcie->name, ret); |
| 428 | return ret; |
| 429 | } |
Pali Rohár | 6f3e57a | 2021-10-22 16:22:14 +0200 | [diff] [blame] | 430 | |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 431 | /* |
| 432 | * Change Class Code of PCI Bridge device to PCI Bridge (0x600400) |
| 433 | * because default value is Memory controller (0x508000) which |
| 434 | * U-Boot cannot recognize as P2P Bridge. |
| 435 | * |
| 436 | * Note that this mvebu PCI Bridge does not have compliant Type 1 |
Pali Rohár | 3166722 | 2021-11-11 16:35:45 +0100 | [diff] [blame] | 437 | * Configuration Space. Header Type is reported as Type 0 and it |
| 438 | * has format of Type 0 config space. |
| 439 | * |
| 440 | * Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34) |
| 441 | * have the same format in Marvell's specification as in PCIe |
| 442 | * specification, but their meaning is totally different and they do |
| 443 | * different things: they are aliased into internal mvebu registers |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 444 | * (e.g. MVPCIE_BAR_LO_OFF) and these should not be changed or |
Pali Rohár | 3166722 | 2021-11-11 16:35:45 +0100 | [diff] [blame] | 445 | * reconfigured by pci device drivers. |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 446 | * |
Pali Rohár | 3166722 | 2021-11-11 16:35:45 +0100 | [diff] [blame] | 447 | * So our driver converts Type 0 config space to Type 1 and reports |
| 448 | * Header Type as Type 1. Access to BAR registers and to non-existent |
| 449 | * Type 1 registers is redirected to the virtual cfgcache[] buffer, |
| 450 | * which avoids changing unrelated registers. |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 451 | */ |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 452 | reg = readl(pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 453 | reg &= ~0xffffff00; |
Pali Rohár | 25781e2 | 2022-02-18 13:18:40 +0100 | [diff] [blame] | 454 | reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; |
Pali Rohár | 1307917 | 2022-02-18 12:25:23 +0100 | [diff] [blame] | 455 | writel(reg, pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); |
Marek Behún | 8903673 | 2021-02-08 23:01:40 +0100 | [diff] [blame] | 456 | |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 457 | /* |
| 458 | * mvebu uses local bus number and local device number to determinate |
| 459 | * type of config request. Type 0 is used if target bus number equals |
| 460 | * local bus number and target device number differs from local device |
| 461 | * number. Type 1 is used if target bus number differs from local bus |
| 462 | * number. And when target bus number equals local bus number and |
| 463 | * target device equals local device number then request is routed to |
| 464 | * PCI Bridge which represent local PCIe Root Port. |
| 465 | * |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 466 | * It means that PCI root and secondary buses shares one bus number |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 467 | * which is configured via local bus number. Determination if config |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 468 | * request should go to root or secondary bus is done based on local |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 469 | * device number. |
| 470 | * |
| 471 | * PCIe is point-to-point bus, so at secondary bus is always exactly one |
| 472 | * device with number 0. So set local device number to 1, it would not |
| 473 | * conflict with any device on secondary bus number and will ensure that |
| 474 | * accessing secondary bus and all buses behind secondary would work |
| 475 | * automatically and correctly. Therefore this configuration of local |
| 476 | * device number implies that setting of local bus number configures |
| 477 | * secondary bus number. Set it to 0 as U-Boot CONFIG_PCI_PNP code will |
| 478 | * later configure it via config write requests to the correct value. |
| 479 | * mvebu_pcie_write_config() catches config write requests which tries |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 480 | * to change secondary bus number and correctly updates local bus number |
| 481 | * based on new secondary bus number. |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 482 | * |
| 483 | * With this configuration is PCI Bridge available at secondary bus as |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 484 | * device number 1. But it must be available at root bus (zero) as device |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 485 | * number 0. So in mvebu_pcie_read_config() and mvebu_pcie_write_config() |
Pali Rohár | 0ef7905 | 2022-02-15 11:34:01 +0100 | [diff] [blame] | 486 | * functions rewrite address to the real one when accessing the root bus. |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 487 | */ |
| 488 | mvebu_pcie_set_local_bus_nr(pcie, 0); |
| 489 | mvebu_pcie_set_local_dev_nr(pcie, 1); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 490 | |
Pali Rohár | ed9bcb9 | 2022-01-13 14:28:04 +0100 | [diff] [blame] | 491 | /* |
| 492 | * Kirkwood arch code already maps mbus windows for PCIe IO and MEM. |
| 493 | * So skip calling mvebu_mbus_add_window_by_id() function as it would |
| 494 | * fail on error "conflicts with another window" which means conflict |
| 495 | * with existing PCIe window mappings. |
| 496 | */ |
| 497 | #ifndef CONFIG_ARCH_KIRKWOOD |
Pali Rohár | ca69af4 | 2021-12-21 12:20:13 +0100 | [diff] [blame] | 498 | if (resource_size(&pcie->mem) && |
| 499 | mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr, |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 500 | (phys_addr_t)pcie->mem.start, |
Pali Rohár | 2aeb942 | 2021-11-11 16:35:43 +0100 | [diff] [blame] | 501 | resource_size(&pcie->mem))) { |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 502 | printf("%s: unable to add mbus window for mem at %08x+%08x\n", |
| 503 | pcie->name, |
Pali Rohár | 2aeb942 | 2021-11-11 16:35:43 +0100 | [diff] [blame] | 504 | (u32)pcie->mem.start, (unsigned)resource_size(&pcie->mem)); |
Pali Rohár | ca69af4 | 2021-12-21 12:20:13 +0100 | [diff] [blame] | 505 | pcie->mem.start = 0; |
| 506 | pcie->mem.end = -1; |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 507 | } |
| 508 | |
Pali Rohár | ca69af4 | 2021-12-21 12:20:13 +0100 | [diff] [blame] | 509 | if (resource_size(&pcie->io) && |
| 510 | mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr, |
Phil Sutter | 09577aa | 2021-01-03 23:06:46 +0100 | [diff] [blame] | 511 | (phys_addr_t)pcie->io.start, |
Pali Rohár | 2aeb942 | 2021-11-11 16:35:43 +0100 | [diff] [blame] | 512 | resource_size(&pcie->io))) { |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 513 | printf("%s: unable to add mbus window for IO at %08x+%08x\n", |
| 514 | pcie->name, |
Pali Rohár | 2aeb942 | 2021-11-11 16:35:43 +0100 | [diff] [blame] | 515 | (u32)pcie->io.start, (unsigned)resource_size(&pcie->io)); |
Pali Rohár | ca69af4 | 2021-12-21 12:20:13 +0100 | [diff] [blame] | 516 | pcie->io.start = 0; |
| 517 | pcie->io.end = -1; |
Phil Sutter | 09577aa | 2021-01-03 23:06:46 +0100 | [diff] [blame] | 518 | } |
Pali Rohár | ed9bcb9 | 2022-01-13 14:28:04 +0100 | [diff] [blame] | 519 | #endif |
Phil Sutter | 09577aa | 2021-01-03 23:06:46 +0100 | [diff] [blame] | 520 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 521 | /* Setup windows and configure host bridge */ |
| 522 | mvebu_pcie_setup_wins(pcie); |
| 523 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 524 | /* PCI memory space */ |
| 525 | pci_set_region(hose->regions + 0, pcie->mem.start, |
Pali Rohár | 2aeb942 | 2021-11-11 16:35:43 +0100 | [diff] [blame] | 526 | pcie->mem.start, resource_size(&pcie->mem), PCI_REGION_MEM); |
Pali Rohár | ca69af4 | 2021-12-21 12:20:13 +0100 | [diff] [blame] | 527 | hose->region_count = 1; |
| 528 | |
| 529 | if (resource_size(&pcie->mem)) { |
| 530 | pci_set_region(hose->regions + hose->region_count, |
| 531 | pcie->mem.start, pcie->mem.start, |
| 532 | resource_size(&pcie->mem), |
| 533 | PCI_REGION_MEM); |
| 534 | hose->region_count++; |
| 535 | } |
| 536 | |
| 537 | if (resource_size(&pcie->io)) { |
| 538 | pci_set_region(hose->regions + hose->region_count, |
| 539 | pcie->io.start, pcie->io.start, |
| 540 | resource_size(&pcie->io), |
| 541 | PCI_REGION_IO); |
| 542 | hose->region_count++; |
| 543 | } |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 544 | |
Pali Rohár | 9e2274d | 2021-10-22 16:22:10 +0200 | [diff] [blame] | 545 | /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */ |
| 546 | pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] = |
| 547 | PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8); |
| 548 | pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] = |
| 549 | PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16); |
| 550 | |
Pali Rohár | 62297ec | 2022-08-05 16:03:41 +0200 | [diff] [blame] | 551 | /* Release PERST# via GPIO when it was defined */ |
| 552 | if (dm_gpio_is_valid(&pcie->reset_gpio)) |
| 553 | dm_gpio_set_value(&pcie->reset_gpio, 0); |
| 554 | |
Pali Rohár | 91d02fb | 2021-12-21 12:20:17 +0100 | [diff] [blame] | 555 | mvebu_pcie_wait_for_link(pcie); |
| 556 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 557 | return 0; |
| 558 | } |
| 559 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 560 | #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) |
| 561 | #define DT_TYPE_IO 0x1 |
| 562 | #define DT_TYPE_MEM32 0x2 |
| 563 | #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF) |
| 564 | #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF) |
| 565 | |
| 566 | static int mvebu_get_tgt_attr(ofnode node, int devfn, |
| 567 | unsigned long type, |
| 568 | unsigned int *tgt, |
| 569 | unsigned int *attr) |
| 570 | { |
| 571 | const int na = 3, ns = 2; |
| 572 | const __be32 *range; |
| 573 | int rlen, nranges, rangesz, pna, i; |
| 574 | |
| 575 | *tgt = -1; |
| 576 | *attr = -1; |
| 577 | |
| 578 | range = ofnode_get_property(node, "ranges", &rlen); |
| 579 | if (!range) |
| 580 | return -EINVAL; |
| 581 | |
Stefan Roese | 24e23bd | 2019-02-11 07:53:34 +0100 | [diff] [blame] | 582 | /* |
| 583 | * Linux uses of_n_addr_cells() to get the number of address cells |
| 584 | * here. Currently this function is only available in U-Boot when |
| 585 | * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in |
| 586 | * general, lets't hardcode the "pna" value in the U-Boot code. |
| 587 | */ |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 588 | pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */ |
| 589 | rangesz = pna + na + ns; |
| 590 | nranges = rlen / sizeof(__be32) / rangesz; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 591 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 592 | for (i = 0; i < nranges; i++, range += rangesz) { |
| 593 | u32 flags = of_read_number(range, 1); |
| 594 | u32 slot = of_read_number(range + 1, 1); |
| 595 | u64 cpuaddr = of_read_number(range + na, pna); |
| 596 | unsigned long rtype; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 597 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 598 | if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO) |
| 599 | rtype = IORESOURCE_IO; |
| 600 | else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32) |
| 601 | rtype = IORESOURCE_MEM; |
| 602 | else |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 603 | continue; |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 604 | |
| 605 | /* |
| 606 | * The Linux code used PCI_SLOT() here, which expects devfn |
| 607 | * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(), |
| 608 | * only expects devfn in 15..8, where its saved in this driver. |
| 609 | */ |
| 610 | if (slot == PCI_DEV(devfn) && type == rtype) { |
| 611 | *tgt = DT_CPUADDR_TO_TARGET(cpuaddr); |
| 612 | *attr = DT_CPUADDR_TO_ATTR(cpuaddr); |
| 613 | return 0; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 614 | } |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 615 | } |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 616 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 617 | return -ENOENT; |
| 618 | } |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 619 | |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 620 | static int mvebu_pcie_port_parse_dt(ofnode node, ofnode parent, struct mvebu_pcie *pcie) |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 621 | { |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 622 | struct fdt_pci_addr pci_addr; |
Pali Rohár | 807292f | 2021-12-21 12:20:14 +0100 | [diff] [blame] | 623 | const u32 *addr; |
Pali Rohár | 5fc93e2 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 624 | u32 num_lanes; |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 625 | int ret = 0; |
Pali Rohár | 807292f | 2021-12-21 12:20:14 +0100 | [diff] [blame] | 626 | int len; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 627 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 628 | /* Get port number, lane number and memory target / attr */ |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 629 | if (ofnode_read_u32(node, "marvell,pcie-port", |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 630 | &pcie->port)) { |
| 631 | ret = -ENODEV; |
| 632 | goto err; |
| 633 | } |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 634 | |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 635 | if (ofnode_read_u32(node, "marvell,pcie-lane", &pcie->lane)) |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 636 | pcie->lane = 0; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 637 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 638 | sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 639 | |
Pali Rohár | 5fc93e2 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 640 | if (!ofnode_read_u32(node, "num-lanes", &num_lanes) && num_lanes == 4) |
| 641 | pcie->is_x4 = true; |
| 642 | |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 643 | /* devfn is in bits [15:8], see PCI_DEV usage */ |
| 644 | ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg", &pci_addr); |
| 645 | if (ret < 0) { |
| 646 | printf("%s: property \"reg\" is invalid\n", pcie->name); |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 647 | goto err; |
| 648 | } |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 649 | pcie->devfn = pci_addr.phys_hi & 0xff00; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 650 | |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 651 | ret = mvebu_get_tgt_attr(parent, pcie->devfn, |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 652 | IORESOURCE_MEM, |
| 653 | &pcie->mem_target, &pcie->mem_attr); |
| 654 | if (ret < 0) { |
| 655 | printf("%s: cannot get tgt/attr for mem window\n", pcie->name); |
| 656 | goto err; |
| 657 | } |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 658 | |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 659 | ret = mvebu_get_tgt_attr(parent, pcie->devfn, |
Phil Sutter | 09577aa | 2021-01-03 23:06:46 +0100 | [diff] [blame] | 660 | IORESOURCE_IO, |
| 661 | &pcie->io_target, &pcie->io_attr); |
| 662 | if (ret < 0) { |
| 663 | printf("%s: cannot get tgt/attr for IO window\n", pcie->name); |
| 664 | goto err; |
| 665 | } |
| 666 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 667 | /* Parse PCIe controller register base from DT */ |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 668 | addr = ofnode_get_property(node, "assigned-addresses", &len); |
Pali Rohár | 807292f | 2021-12-21 12:20:14 +0100 | [diff] [blame] | 669 | if (!addr) { |
| 670 | printf("%s: property \"assigned-addresses\" not found\n", pcie->name); |
| 671 | ret = -FDT_ERR_NOTFOUND; |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 672 | goto err; |
Pali Rohár | 807292f | 2021-12-21 12:20:14 +0100 | [diff] [blame] | 673 | } |
| 674 | |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 675 | pcie->base = (void *)(u32)ofnode_translate_address(node, addr); |
Pali Rohár | bb26c4a | 2021-12-21 12:20:15 +0100 | [diff] [blame] | 676 | pcie->intregs = (u32)pcie->base - fdt32_to_cpu(addr[2]); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 677 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 678 | return 0; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 679 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 680 | err: |
| 681 | return ret; |
| 682 | } |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 683 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 684 | static const struct dm_pci_ops mvebu_pcie_ops = { |
| 685 | .read_config = mvebu_pcie_read_config, |
| 686 | .write_config = mvebu_pcie_write_config, |
| 687 | }; |
Phil Sutter | 68010aa | 2015-12-25 14:41:20 +0100 | [diff] [blame] | 688 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 689 | static struct driver pcie_mvebu_drv = { |
| 690 | .name = "pcie_mvebu", |
| 691 | .id = UCLASS_PCI, |
| 692 | .ops = &mvebu_pcie_ops, |
| 693 | .probe = mvebu_pcie_probe, |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 694 | .plat_auto = sizeof(struct mvebu_pcie), |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 695 | }; |
| 696 | |
| 697 | /* |
| 698 | * Use a MISC device to bind the n instances (child nodes) of the |
| 699 | * PCIe base controller in UCLASS_PCI. |
| 700 | */ |
| 701 | static int mvebu_pcie_bind(struct udevice *parent) |
| 702 | { |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 703 | struct mvebu_pcie **ports_pcie; |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 704 | struct mvebu_pcie *pcie; |
| 705 | struct uclass_driver *drv; |
| 706 | struct udevice *dev; |
Pali Rohár | ca69af4 | 2021-12-21 12:20:13 +0100 | [diff] [blame] | 707 | struct resource mem; |
| 708 | struct resource io; |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 709 | int ports_count, i; |
| 710 | ofnode *ports_nodes; |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 711 | ofnode subnode; |
| 712 | |
Pali Rohár | ac2ee55 | 2021-10-22 16:22:15 +0200 | [diff] [blame] | 713 | /* Lookup pci driver */ |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 714 | drv = lists_uclass_lookup(UCLASS_PCI); |
| 715 | if (!drv) { |
| 716 | puts("Cannot find PCI driver\n"); |
| 717 | return -ENOENT; |
| 718 | } |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 719 | |
| 720 | ports_count = ofnode_get_child_count(dev_ofnode(parent)); |
| 721 | ports_pcie = calloc(ports_count, sizeof(*ports_pcie)); |
| 722 | ports_nodes = calloc(ports_count, sizeof(*ports_nodes)); |
| 723 | if (!ports_pcie || !ports_nodes) { |
| 724 | free(ports_pcie); |
| 725 | free(ports_nodes); |
| 726 | return -ENOMEM; |
| 727 | } |
| 728 | ports_count = 0; |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 729 | |
Pali Rohár | ed9bcb9 | 2022-01-13 14:28:04 +0100 | [diff] [blame] | 730 | #ifdef CONFIG_ARCH_KIRKWOOD |
| 731 | mem.start = KW_DEFADR_PCI_MEM; |
| 732 | mem.end = KW_DEFADR_PCI_MEM + KW_DEFADR_PCI_MEM_SIZE - 1; |
| 733 | io.start = KW_DEFADR_PCI_IO; |
| 734 | io.end = KW_DEFADR_PCI_IO + KW_DEFADR_PCI_IO_SIZE - 1; |
| 735 | #else |
Pali Rohár | ca69af4 | 2021-12-21 12:20:13 +0100 | [diff] [blame] | 736 | mem.start = MBUS_PCI_MEM_BASE; |
| 737 | mem.end = MBUS_PCI_MEM_BASE + MBUS_PCI_MEM_SIZE - 1; |
| 738 | io.start = MBUS_PCI_IO_BASE; |
| 739 | io.end = MBUS_PCI_IO_BASE + MBUS_PCI_IO_SIZE - 1; |
Pali Rohár | ed9bcb9 | 2022-01-13 14:28:04 +0100 | [diff] [blame] | 740 | #endif |
Pali Rohár | ca69af4 | 2021-12-21 12:20:13 +0100 | [diff] [blame] | 741 | |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 742 | /* First phase: Fill mvebu_pcie struct for each port */ |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 743 | ofnode_for_each_subnode(subnode, dev_ofnode(parent)) { |
Simon Glass | 2e4938b | 2022-09-06 20:27:17 -0600 | [diff] [blame] | 744 | if (!ofnode_is_enabled(subnode)) |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 745 | continue; |
| 746 | |
| 747 | pcie = calloc(1, sizeof(*pcie)); |
| 748 | if (!pcie) |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 749 | continue; |
| 750 | |
| 751 | if (mvebu_pcie_port_parse_dt(subnode, dev_ofnode(parent), pcie) < 0) { |
| 752 | free(pcie); |
| 753 | continue; |
| 754 | } |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 755 | |
Pali Rohár | ca69af4 | 2021-12-21 12:20:13 +0100 | [diff] [blame] | 756 | /* |
| 757 | * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped |
| 758 | * into SoCs address space. Each controller will map 128M of MEM |
| 759 | * and 64K of I/O space when registered. |
| 760 | */ |
| 761 | |
| 762 | if (resource_size(&mem) >= SZ_128M) { |
| 763 | pcie->mem.start = mem.start; |
| 764 | pcie->mem.end = mem.start + SZ_128M - 1; |
| 765 | mem.start += SZ_128M; |
| 766 | } else { |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 767 | printf("%s: unable to assign mbus window for mem\n", pcie->name); |
Pali Rohár | ca69af4 | 2021-12-21 12:20:13 +0100 | [diff] [blame] | 768 | pcie->mem.start = 0; |
| 769 | pcie->mem.end = -1; |
| 770 | } |
| 771 | |
| 772 | if (resource_size(&io) >= SZ_64K) { |
| 773 | pcie->io.start = io.start; |
| 774 | pcie->io.end = io.start + SZ_64K - 1; |
| 775 | io.start += SZ_64K; |
| 776 | } else { |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 777 | printf("%s: unable to assign mbus window for io\n", pcie->name); |
Pali Rohár | ca69af4 | 2021-12-21 12:20:13 +0100 | [diff] [blame] | 778 | pcie->io.start = 0; |
| 779 | pcie->io.end = -1; |
| 780 | } |
| 781 | |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 782 | ports_pcie[ports_count] = pcie; |
| 783 | ports_nodes[ports_count] = subnode; |
| 784 | ports_count++; |
| 785 | } |
| 786 | |
| 787 | /* Second phase: Setup all PCIe links (do not enable them yet) */ |
| 788 | for (i = 0; i < ports_count; i++) |
| 789 | mvebu_pcie_setup_link(ports_pcie[i]); |
| 790 | |
| 791 | /* Third phase: Enable all PCIe links and create for each UCLASS_PCI device */ |
| 792 | for (i = 0; i < ports_count; i++) { |
| 793 | pcie = ports_pcie[i]; |
| 794 | subnode = ports_nodes[i]; |
| 795 | |
| 796 | /* |
| 797 | * PCIe link can be enabled only after all PCIe links were |
| 798 | * properly configured. This is because more PCIe links shares |
| 799 | * one enable bit and some PCIe links cannot be enabled |
| 800 | * individually. |
| 801 | */ |
| 802 | if (mvebu_pcie_enable_link(pcie, subnode) < 0) { |
| 803 | free(pcie); |
| 804 | continue; |
| 805 | } |
| 806 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 807 | /* Create child device UCLASS_PCI and bind it */ |
Simon Glass | 884870f | 2020-11-28 17:50:01 -0700 | [diff] [blame] | 808 | device_bind(parent, &pcie_mvebu_drv, pcie->name, pcie, subnode, |
| 809 | &dev); |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 810 | } |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 811 | |
Pali Rohár | 3f6890d | 2021-12-21 12:20:16 +0100 | [diff] [blame] | 812 | free(ports_pcie); |
| 813 | free(ports_nodes); |
| 814 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 815 | return 0; |
Anton Schubert | 98530e9 | 2015-08-11 11:54:01 +0200 | [diff] [blame] | 816 | } |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 817 | |
| 818 | static const struct udevice_id mvebu_pcie_ids[] = { |
| 819 | { .compatible = "marvell,armada-xp-pcie" }, |
| 820 | { .compatible = "marvell,armada-370-pcie" }, |
Pali Rohár | ed9bcb9 | 2022-01-13 14:28:04 +0100 | [diff] [blame] | 821 | { .compatible = "marvell,kirkwood-pcie" }, |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 822 | { } |
| 823 | }; |
| 824 | |
| 825 | U_BOOT_DRIVER(pcie_mvebu_base) = { |
| 826 | .name = "pcie_mvebu_base", |
| 827 | .id = UCLASS_MISC, |
| 828 | .of_match = mvebu_pcie_ids, |
| 829 | .bind = mvebu_pcie_bind, |
| 830 | }; |