blob: 4abc8026b4daf0e473c70606dd9e075be328cef3 [file] [log] [blame]
Wenyou Yang8c772bd2016-07-20 17:55:12 +08001config CLK_AT91
2 bool "AT91 clock drivers"
3 depends on CLK
Wenyou Yang9a71d392016-09-27 11:00:29 +08004 select MISC
Wenyou Yang8c772bd2016-07-20 17:55:12 +08005 help
6 This option is used to enable the AT91 clock driver.
7 The driver supports the AT91 clock generator, including
8 the oscillators and PLLs, such as main clock, slow clock,
9 PLLA, UTMI PLL. Clocks can also be a source clock of other
10 clocks a tree structure, such as master clock, usb device
11 clock, matrix clock and generic clock.
12 Devices can use a common clock API to request a particular
13 clock, enable it and get its rate.
14
15config AT91_UTMI
16 bool "Support UTMI PLL Clock"
Wenyou Yange54b4f02017-11-17 14:46:43 +080017 depends on CLK_AT91
Wenyou Yang6b66b922017-09-05 18:30:07 +080018 select REGMAP
Wenyou Yange54b4f02017-11-17 14:46:43 +080019 select SPL_REGMAP if SPL_DM
Wenyou Yang6b66b922017-09-05 18:30:07 +080020 select SYSCON
Wenyou Yange54b4f02017-11-17 14:46:43 +080021 select SPL_SYSCON if SPL_DM
Wenyou Yang8c772bd2016-07-20 17:55:12 +080022 help
23 This option is used to enable the AT91 UTMI PLL clock
24 driver. It is the clock provider of USB, and UPLLCK is the
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
27 fast crystal oscillator to meet the frequency accuracy
28 required by USB.
29
Wenyou Yang22cb2372018-02-09 11:34:50 +080030config AT91_USB_CLK
31 bool "Support USB OHCI Input Clock"
32 depends on CLK_AT91
33 help
34 This option is used to enable the USB Input Clock, from
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
36 and USBDIV field of the PMC_USB register.
37
Wenyou Yang8c772bd2016-07-20 17:55:12 +080038config AT91_H32MX
39 bool "Support H32MX 32-bit Matrix Clock"
40 depends on CLK_AT91
41 help
42 This option is used to enable the AT91 H32MX matrixes
43 clock driver. There are H64MX and H32MX matrixes clocks,
44 H64MX 64-bit matrix clocks are MCK. The H32MX 32-bit
45 matrix clock is to be configured as MCK if MCK does not
46 exceed 83 MHz, else it is to be configured as MCK/2.
47
48config AT91_GENERIC_CLK
49 bool "Support Generic Clock"
50 depends on CLK_AT91
51 help
52 This option is used to enable the AT91 generic clock
53 driver. Some peripherals may need a second clock source
54 that may be different from the system clock. This second
55 clock is the generic clock (GCLK) and is managed by
56 the PMC via PMC_PCR register.
Claudiu Beznea923ac872020-09-07 17:46:42 +030057
58config AT91_SAM9X60_PLL
59 bool "PLL support for SAM9X60 SoCs"
60 depends on CLK_AT91
61 help
62 This option is used to enable the AT91 SAM9X60's PLL clock
63 driver.