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git01.mediatek.com / filogic / uboot / d26d67cda5a1fa85a13f8669fc85550bd5680216 / . / board / siemens / SCM / scm.c
blob: 8783aafe9a124a16797f4275747572409f97f974 [file] [log] [blame]
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ioports.h>
26#include <mpc8260.h>
27
28#include "scm.h"
29
Wolfgang Denk6405a152006-03-31 18:32:53 +0200[diff] [blame]30DECLARE_GLOBAL_DATA_PTR;
31
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]32static void config_scoh_cs(void);
33extern int fpga_init(void);
34
35#if 0
36#define DEBUGF(fmt,args...) printf (fmt ,##args)
37#else
38#define DEBUGF(fmt,args...)
39#endif
40
41/*
42 * I/O Port configuration table
43 *
44 * if conf is 1, then that port pin will be configured at boot time
45 * according to the five values podr/pdir/ppar/psor/pdat for that entry
46 */
47
48const iop_conf_t iop_conf_tab[4][32] = {
49
50 /* Port A configuration */
51 { /* conf ppar psor pdir podr pdat */
52 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
53 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
54 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
55 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
56 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
57 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
58 /* PA25 */ { 0, 0, 0, 1, 0, 0 },
59 /* PA24 */ { 0, 0, 0, 1, 0, 0 },
60 /* PA23 */ { 0, 0, 0, 1, 0, 0 },
61 /* PA22 */ { 0, 0, 0, 1, 0, 0 },
62 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
63 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
64 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
65 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
66 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
67 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1]*/
68 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
69 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
70 /* PA13 */ { 0, 0, 0, 1, 0, 0 },
71 /* PA12 */ { 0, 0, 0, 1, 0, 0 },
72 /* PA11 */ { 0, 0, 0, 1, 0, 0 },
73 /* PA10 */ { 0, 0, 0, 1, 0, 0 },
74 /* PA9 */ { 1, 1, 1, 1, 0, 0 }, /* TDM_A1 L1TXD0 */
75 /* PA8 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RXD0 */
76 /* PA7 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1TSYNC */
77 /* PA6 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RSYNC */
78 /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* FIOX_FPGA_PR */
79 /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* DOHM_FPGA_PR */
80 /* PA3 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK4 */
81 /* PA2 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK4 */
82 /* PA1 */ { 0, 0, 0, 1, 0, 0 },
83 /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* BUSY */
84 },
85
86 /* Port B configuration */
87 { /* conf ppar psor pdir podr pdat */
88 /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MIN */
89 /* PB30 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MAJ */
90 /* PB29 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MIN */
91 /* PB28 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MAJ */
92 /* PB27 */ { 0, 1, 0, 0, 0, 0 },
93 /* PB26 */ { 0, 1, 0, 0, 0, 0 },
94 /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* LED_GREEN_L */
95 /* PB24 */ { 1, 0, 0, 1, 0, 0 }, /* LED_RED_L */
96 /* PB23 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TXD */
97 /* PB22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RXD */
98 /* PB21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TSYNC */
99 /* PB20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RSYNC */
100 /* PB19 */ { 1, 0, 0, 0, 0, 0 }, /* UID */
101 /* PB18 */ { 0, 1, 0, 0, 0, 0 },
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]102 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
103 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
104 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
105 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
106 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
107 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
108 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
109 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
110 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
111 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
112 /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
113 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
114 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
115 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]116 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
117 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
118 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
119 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
120 },
121
122 /* Port C configuration */
123 { /* conf ppar psor pdir podr pdat */
124 /* PC31 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK1 */
125 /* PC30 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK1 */
126 /* PC29 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK3 */
127 /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK3 */
128 /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK2 */
129 /* PC26 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK2 */
130 /* PC25 */ { 0, 0, 0, 1, 0, 0 },
131 /* PC24 */ { 0, 0, 0, 1, 0, 0 },
132 /* PC23 */ { 0, 1, 0, 1, 0, 0 },
133 /* PC22 */ { 0, 1, 0, 0, 0, 0 },
134 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
135 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
136 /* PC19 */ { 0, 1, 0, 0, 0, 0 },
137 /* PC18 */ { 0, 1, 0, 0, 0, 0 },
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]138 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
139 /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]140 /* PC15 */ { 0, 0, 0, 1, 0, 0 },
141 /* PC14 */ { 0, 1, 0, 0, 0, 0 },
142 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* RES_PHY_L */
143 /* PC12 */ { 0, 0, 0, 1, 0, 0 },
144 /* PC11 */ { 0, 0, 0, 1, 0, 0 },
145 /* PC10 */ { 0, 0, 0, 1, 0, 0 },
146 /* PC9 */ { 0, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TSYNC */
147 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* FEP_RDY */
148 /* PC7 */ { 0, 0, 0, 0, 0, 0 },
149 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* UC4_ALARM_L */
150 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* UC3_ALARM_L */
151 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* UC2_ALARM_L */
152 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* RES_MISC_L */
153 /* PC2 */ { 0, 0, 0, 1, 0, 0 }, /* RES_OH_L */
154 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* RES_DOHM_L */
155 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* RES_FIOX_L */
156 },
157
158 /* Port D configuration */
159 { /* conf ppar psor pdir podr pdat */
160 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
161 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
162 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_F */
163 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_F */
164 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_D */
165 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_D */
166 /* PD25 */ { 0, 0, 0, 1, 0, 0 },
167 /* PD24 */ { 0, 0, 0, 1, 0, 0 },
168 /* PD23 */ { 0, 0, 0, 1, 0, 0 },
169 /* PD22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TXD */
170 /* PD21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RXD */
171 /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */
172 /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPISEL */
173 /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPICLK */
174 /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSI */
175 /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSO */
176#if defined(CONFIG_SOFT_I2C)
177 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
178 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
179#else
180#if defined(CONFIG_HARD_I2C)
181 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
182 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
183#else /* normal I/O port pins */
184 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
185 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
186#endif
187#endif
188 /* PD13 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TXD */
189 /* PD12 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RXD */
190 /* PD11 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TSYNC */
191 /* PD10 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RSYNC */
192 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
193 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
194 /* PD7 */ { 0, 0, 0, 1, 0, 1 },
195 /* PD6 */ { 0, 0, 0, 1, 0, 1 },
196 /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_F */
197 /* PD4 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_D */
198 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
199 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
200 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
201 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
202 }
203};
204
205/* ------------------------------------------------------------------------- */
206
207/* Check Board Identity:
208 */
209int checkboard (void)
210{
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200[diff] [blame]211 char str[64];
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]212 int i = getenv_r ("serial#", str, sizeof (str));
213
214 puts ("Board: ");
215
216 if (!i || strncmp (str, "TQM8260", 7)) {
217 puts ("### No HW ID - assuming TQM8260\n");
218 return (0);
219 }
220
221 puts (str);
222 putc ('\n');
223
224 return 0;
225}
226
227/* ------------------------------------------------------------------------- */
228
229/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
230 *
231 * This routine performs standard 8260 initialization sequence
232 * and calculates the available memory size. It may be called
233 * several times to try different SDRAM configurations on both
234 * 60x and local buses.
235 */
236static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
237 ulong orx, volatile uchar * base)
238{
239 volatile uchar c = 0xff;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]240 volatile uint *sdmr_ptr;
241 volatile uint *orx_ptr;
wdenk87249ba2004-01-06 22:38:14 +0000[diff] [blame]242 ulong maxsize, size;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]243 int i;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]244
245 /* We must be able to test a location outsize the maximum legal size
246 * to find out THAT we are outside; but this address still has to be
247 * mapped by the controller. That means, that the initial mapping has
248 * to be (at least) twice as large as the maximum expected size.
249 */
250 maxsize = (1 + (~orx | 0x7fff)) / 2;
251
252 /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
253 * we are configuring CS1 if base != 0
254 */
255 sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
256 orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
257
258 *orx_ptr = orx;
259
260 /*
261 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
262 *
263 * "At system reset, initialization software must set up the
264 * programmable parameters in the memory controller banks registers
265 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
266 * system software should execute the following initialization sequence
267 * for each SDRAM device.
268 *
269 * 1. Issue a PRECHARGE-ALL-BANKS command
270 * 2. Issue eight CBR REFRESH commands
271 * 3. Issue a MODE-SET command to initialize the mode register
272 *
273 * The initial commands are executed by setting P/LSDMR[OP] and
274 * accessing the SDRAM with a single-byte transaction."
275 *
276 * The appropriate BRx/ORx registers have already been set when we
277 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
278 */
279
280 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
281 *base = c;
282
283 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
284 for (i = 0; i < 8; i++)
285 *base = c;
286
287 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
288 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
289
290 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
291 *base = c;
292
wdenk87249ba2004-01-06 22:38:14 +0000[diff] [blame]293 size = get_ram_size((long *)base, maxsize);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]294
wdenk87249ba2004-01-06 22:38:14 +0000[diff] [blame]295 *orx_ptr = orx | ~(size - 1);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]296
wdenk87249ba2004-01-06 22:38:14 +0000[diff] [blame]297 return (size);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]298}
299
300/*
301 * Test Power-On-Reset.
302 */
303int power_on_reset (void)
304{
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]305 /* Test Reset Status Register */
306 return gd->reset_status & RSR_CSRS ? 0 : 1;
307}
308
309long int initdram (int board_type)
310{
311 volatile immap_t *immap = (immap_t *) CFG_IMMR;
312 volatile memctl8260_t *memctl = &immap->im_memctl;
313
314#ifndef CFG_RAMBOOT
315 long size8, size9;
316#endif
317 long psize, lsize;
318
319 psize = 16 * 1024 * 1024;
320 lsize = 0;
321
322 memctl->memc_psrt = CFG_PSRT;
323 memctl->memc_mptpr = CFG_MPTPR;
324
325#if 0 /* Just for debugging */
326#define prt_br_or(brX,orX) do { \
327 ulong start = memctl->memc_ ## brX & 0xFFFF8000; \
328 ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \
329 printf ("\n" \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]330 #brX " 0x%08x " #orX " 0x%08x " \
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]331 "==> 0x%08lx ... 0x%08lx = %ld MB\n", \
332 memctl->memc_ ## brX, memctl->memc_ ## orX, \
333 start, start+sizem, (sizem+1)>>20); \
334 } while (0)
335 prt_br_or (br0, or0);
336 prt_br_or (br1, or1);
337 prt_br_or (br2, or2);
338 prt_br_or (br3, or3);
339#endif
340
341#ifndef CFG_RAMBOOT
342 /* 60x SDRAM setup:
343 */
344 size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
345 (uchar *) CFG_SDRAM_BASE);
346 size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
347 (uchar *) CFG_SDRAM_BASE);
348
349 if (size8 < size9) {
350 psize = size9;
351 printf ("(60x:9COL - %ld MB, ", psize >> 20);
352 } else {
353 psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
354 (uchar *) CFG_SDRAM_BASE);
355 printf ("(60x:8COL - %ld MB, ", psize >> 20);
356 }
357
358 /* Local SDRAM setup:
359 */
360#ifdef CFG_INIT_LOCAL_SDRAM
361 memctl->memc_lsrt = CFG_LSRT;
362 size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
363 (uchar *) SDRAM_BASE2_PRELIM);
364 size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
365 (uchar *) SDRAM_BASE2_PRELIM);
366
367 if (size8 < size9) {
368 lsize = size9;
369 printf ("Local:9COL - %ld MB) using ", lsize >> 20);
370 } else {
371 lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
372 (uchar *) SDRAM_BASE2_PRELIM);
373 printf ("Local:8COL - %ld MB) using ", lsize >> 20);
374 }
375
376#if 0
377 /* Set up BR2 so that the local SDRAM goes
378 * right after the 60x SDRAM
379 */
380 memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
381 (CFG_SDRAM_BASE + psize);
382#endif
383#endif /* CFG_INIT_LOCAL_SDRAM */
384#endif /* CFG_RAMBOOT */
385
386 icache_enable ();
387
388 config_scoh_cs ();
389
390 return (psize);
391}
392
393/* ------------------------------------------------------------------------- */
394
395static void config_scoh_cs (void)
396{
397 volatile immap_t *immr = (immap_t *) CFG_IMMR;
398 volatile memctl8260_t *memctl = &immr->im_memctl;
399 volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE;
400 volatile uint tmp, i;
401
402 /* Initialize OR3 / BR3 for CAN Bus Controller 0 */
403 memctl->memc_or3 = CFG_CAN0_OR3;
404 memctl->memc_br3 = CFG_CAN0_BR3;
405 /* Initialize OR4 / BR4 for CAN Bus Controller 1 */
406 memctl->memc_or4 = CFG_CAN1_OR4;
407 memctl->memc_br4 = CFG_CAN1_BR4;
408
409 /* Initialize MAMR to write in the array at address 0x0 */
410 memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
411
412 /* Initialize UPMA for CAN: single read */
413 memctl->memc_mdr = 0xcffeec00;
414 udelay (1); /* Necessary to have the data correct in the UPM array!!!! */
415 /* The read on the CAN controller write the data of mdr in UPMA array. */
416 /* The index to the array will be incremented automatically
417 through this read */
418 tmp = can->cpu_interface;
419
420 memctl->memc_mdr = 0x0ffcec00;
421 udelay (1);
422 tmp = can->cpu_interface;
423
424 memctl->memc_mdr = 0x0ffcec00;
425 udelay (1);
426 tmp = can->cpu_interface;
427
428 memctl->memc_mdr = 0x0ffcec00;
429 udelay (1);
430 tmp = can->cpu_interface;
431
432 memctl->memc_mdr = 0x0ffcec00;
433 udelay (1);
434 tmp = can->cpu_interface;
435
436 memctl->memc_mdr = 0x0ffcfc00;
437 udelay (1);
438 tmp = can->cpu_interface;
439
440 memctl->memc_mdr = 0x0ffcfc00;
441 udelay (1);
442 tmp = can->cpu_interface;
443
444 memctl->memc_mdr = 0xfffdec07;
445 udelay (1);
446 tmp = can->cpu_interface;
447
448
449 /* Initialize MAMR to write in the array at address 0x18 */
450 memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
451
452 /* Initialize UPMA for CAN: single write */
453 memctl->memc_mdr = 0xfcffec00;
454 udelay (1);
455 tmp = can->cpu_interface;
456
457 memctl->memc_mdr = 0x00ffec00;
458 udelay (1);
459 tmp = can->cpu_interface;
460
461 memctl->memc_mdr = 0x00ffec00;
462 udelay (1);
463 tmp = can->cpu_interface;
464
465 memctl->memc_mdr = 0x00ffec00;
466 udelay (1);
467 tmp = can->cpu_interface;
468
469 memctl->memc_mdr = 0x00ffec00;
470 udelay (1);
471 tmp = can->cpu_interface;
472
473 memctl->memc_mdr = 0x00fffc00;
474 udelay (1);
475 tmp = can->cpu_interface;
476
477 memctl->memc_mdr = 0x00fffc00;
478 udelay (1);
479 tmp = can->cpu_interface;
480
481 memctl->memc_mdr = 0x30ffec07;
482 udelay (1);
483 tmp = can->cpu_interface;
484
485 /* Initialize MAMR */
486 memctl->memc_mamr = MxMR_GPL_x4DIS; /* GPL_B4 ouput line Disable */
487
488
489 /* Initialize OR5 / BR5 for the extended EEPROM Bank0 */
490 memctl->memc_or5 = CFG_EXTPROM_OR5;
491 memctl->memc_br5 = CFG_EXTPROM_BR5;
492 /* Initialize OR6 / BR6 for the extended EEPROM Bank1 */
493 memctl->memc_or6 = CFG_EXTPROM_OR6;
494 memctl->memc_br6 = CFG_EXTPROM_BR6;
495
496 /* Initialize OR7 / BR7 for the Glue Logic */
497 memctl->memc_or7 = CFG_FIOX_OR7;
498 memctl->memc_br7 = CFG_FIOX_BR7;
499
500 /* Initialize OR8 / BR8 for the DOH Logic */
501 memctl->memc_or8 = CFG_FDOHM_OR8;
502 memctl->memc_br8 = CFG_FDOHM_BR8;
503
504 DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);
505 DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);
506 DEBUGF ("OR2 %08x BR2 %08x\n", memctl->memc_or2, memctl->memc_br2);
507 DEBUGF ("OR3 %08x BR3 %08x\n", memctl->memc_or3, memctl->memc_br3);
508 DEBUGF ("OR4 %08x BR4 %08x\n", memctl->memc_or4, memctl->memc_br4);
509 DEBUGF ("OR5 %08x BR5 %08x\n", memctl->memc_or5, memctl->memc_br5);
510 DEBUGF ("OR6 %08x BR6 %08x\n", memctl->memc_or6, memctl->memc_br6);
511 DEBUGF ("OR7 %08x BR7 %08x\n", memctl->memc_or7, memctl->memc_br7);
512 DEBUGF ("OR8 %08x BR8 %08x\n", memctl->memc_or8, memctl->memc_br8);
513
514 DEBUGF ("UPMA addr 0x0\n");
515 memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
516 for (i = 0; i < 0x8; i++) {
517 tmp = can->cpu_interface;
518 udelay (1);
519 DEBUGF (" %08x ", memctl->memc_mdr);
520 }
521 DEBUGF ("\nUPMA addr 0x18\n");
522 memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
523 for (i = 0; i < 0x8; i++) {
524 tmp = can->cpu_interface;
525 udelay (1);
526 DEBUGF (" %08x ", memctl->memc_mdr);
527 }
528 DEBUGF ("\n");
529 memctl->memc_mamr = MxMR_GPL_x4DIS;
530}
531
532/* ------------------------------------------------------------------------- */
533
534int misc_init_r (void)
535{
536 fpga_init ();
537 return (0);
538}
539
540/* ------------------------------------------------------------------------- */