blob: 8d3ff6aab7eac4d30b00103e08ae78712362fa57 [file] [log] [blame]
wdenk4989f872004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2003
3 * Texas Instruments.
4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
6 *
7 * (C) Copyright 2004
8 * ARM Ltd.
9 * Philippe Robin, <philippe.robin@arm.com>
10 * Configuration for Versatile PB.
11 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
wdenk4989f872004-03-14 15:06:13 +000013 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * High Level Configuration Options
20 * (easy to change)
21 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020022#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
wdenk4989f872004-03-14 15:06:13 +000023#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020024#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
wdenk4989f872004-03-14 15:06:13 +000025
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020026#define CONFIG_SYS_MEMTEST_START 0x100000
27#define CONFIG_SYS_MEMTEST_END 0x10000000
28#define CONFIG_SYS_HZ (1000000 / 256)
29#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */
wdenk4989f872004-03-14 15:06:13 +000030
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020031#define CONFIG_SYS_TIMER_INTERVAL 10000
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020032#define CONFIG_SYS_TIMER_RELOAD (CONFIG_SYS_TIMER_INTERVAL >> 4)
33#define CONFIG_SYS_TIMER_CTRL 0x84 /* Enable, Clock / 16 */
wdenk4989f872004-03-14 15:06:13 +000034
35/*
36 * control registers
37 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020038#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
wdenk4989f872004-03-14 15:06:13 +000039
40/*
41 * System controller bit assignment
42 */
43#define VERSATILE_REFCLK 0
44#define VERSATILE_TIMCLK 1
45
46#define VERSATILE_TIMER1_EnSel 15
47#define VERSATILE_TIMER2_EnSel 17
48#define VERSATILE_TIMER3_EnSel 19
49#define VERSATILE_TIMER4_EnSel 21
50
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020051#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenk4989f872004-03-14 15:06:13 +000052#define CONFIG_SETUP_MEMORY_TAGS 1
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020053#define CONFIG_MISC_INIT_R 1
wdenk4989f872004-03-14 15:06:13 +000054/*
55 * Size of malloc() pool
56 */
Stefano Babic491ff7f2011-06-24 03:04:38 +000057#define CONFIG_ENV_SIZE 8192
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020058#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
wdenk4989f872004-03-14 15:06:13 +000059
60/*
61 * Hardware drivers
62 */
63
Ben Warren0fd6aae2009-10-04 22:37:03 -070064#define CONFIG_SMC91111
wdenk4989f872004-03-14 15:06:13 +000065#define CONFIG_SMC_USE_32_BIT
Wolfgang Denka1be4762008-05-20 16:00:29 +020066#define CONFIG_SMC91111_BASE 0x10010000
wdenk4989f872004-03-14 15:06:13 +000067#undef CONFIG_SMC91111_EXT_PHY
68
69/*
70 * NS16550 Configuration
71 */
Andreas Engel0813b122008-09-08 14:30:53 +020072#define CONFIG_PL011_SERIAL
wdenkda04a8b2004-08-02 23:22:59 +000073#define CONFIG_PL011_CLOCK 24000000
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020074#define CONFIG_PL01x_PORTS \
75 {(void *)CONFIG_SYS_SERIAL0, \
76 (void *)CONFIG_SYS_SERIAL1 }
wdenk4989f872004-03-14 15:06:13 +000077#define CONFIG_CONS_INDEX 0
wdenkda04a8b2004-08-02 23:22:59 +000078
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020079#define CONFIG_BAUDRATE 38400
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080#define CONFIG_SYS_SERIAL0 0x101F1000
81#define CONFIG_SYS_SERIAL1 0x101F2000
wdenk4989f872004-03-14 15:06:13 +000082
Jon Loeliger03bfcb92007-07-04 22:33:46 -050083/*
84 * Command line configuration.
85 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020086#define CONFIG_CMD_BDI
Jon Loeliger03bfcb92007-07-04 22:33:46 -050087#define CONFIG_CMD_DHCP
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020088#define CONFIG_CMD_FLASH
Jon Loeliger03bfcb92007-07-04 22:33:46 -050089#define CONFIG_CMD_IMI
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020090#define CONFIG_CMD_MEMORY
Jon Loeliger03bfcb92007-07-04 22:33:46 -050091#define CONFIG_CMD_NET
92#define CONFIG_CMD_PING
Mike Frysinger78dcaf42009-01-28 19:08:14 -050093#define CONFIG_CMD_SAVEENV
wdenk4989f872004-03-14 15:06:13 +000094
Jon Loeligerc6d535a2007-07-09 21:57:31 -050095/*
96 * BOOTP options
97 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020098#define CONFIG_BOOTP_BOOTPATH
Jon Loeligerc6d535a2007-07-09 21:57:31 -050099#define CONFIG_BOOTP_GATEWAY
100#define CONFIG_BOOTP_HOSTNAME
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200101#define CONFIG_BOOTP_SUBNETMASK
wdenk4989f872004-03-14 15:06:13 +0000102
103#define CONFIG_BOOTDELAY 2
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200104#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\
105 "netdev=25,0,0xf1010000,0xf1010010,eth0"
wdenk4989f872004-03-14 15:06:13 +0000106
107/*
108 * Static configuration when assigning fixed address
109 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200110#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */
wdenk4989f872004-03-14 15:06:13 +0000111
112/*
113 * Miscellaneous configurable options
114 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200115#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200116#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD1b5092d2009-05-02 11:53:49 +0200117/* Monitor Command Prompt */
118#ifdef CONFIG_ARCH_VERSATILE_AB
119# define CONFIG_SYS_PROMPT "VersatileAB # "
120#else
121# define CONFIG_SYS_PROMPT "VersatilePB # "
122#endif
wdenk4989f872004-03-14 15:06:13 +0000123/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200124#define CONFIG_SYS_PBSIZE \
125 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
126#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
127#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk4989f872004-03-14 15:06:13 +0000128
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
wdenk4989f872004-03-14 15:06:13 +0000130
131/*-----------------------------------------------------------------------
wdenk4989f872004-03-14 15:06:13 +0000132 * Physical Memory Map
133 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200134#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
135#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
136#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200137#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
wdenk4989f872004-03-14 15:06:13 +0000138
Stefano Babic491ff7f2011-06-24 03:04:38 +0000139#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
140#define CONFIG_SYS_INIT_RAM_ADDR 0x00800000
141#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF
142#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
143 GENERATED_GBL_DATA_SIZE)
144#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
145 CONFIG_SYS_GBL_DATA_OFFSET)
146
147#define CONFIG_BOARD_EARLY_INIT_F
148
wdenk4989f872004-03-14 15:06:13 +0000149/*-----------------------------------------------------------------------
150 * FLASH and environment organization
151 */
Stefano Babic491ff7f2011-06-24 03:04:38 +0000152#ifdef CONFIG_ARCH_VERSATILE_QEMU
153#define CONFIG_SYS_TEXT_BASE 0x10000
154#define CONFIG_SYS_NO_FLASH
155#define CONFIG_ENV_IS_NOWHERE
156#define CONFIG_SYS_MONITOR_LEN 0x80000
157#else
158#define CONFIG_SYS_TEXT_BASE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200159/*
160 * Use the CFI flash driver for ease of use
161 */
162#define CONFIG_SYS_FLASH_CFI
163#define CONFIG_FLASH_CFI_DRIVER
164#define CONFIG_ENV_IS_IN_FLASH 1
165/*
166 * System control register
167 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200168#define VERSATILE_SYS_BASE 0x10000000
169#define VERSATILE_SYS_FLASH_OFFSET 0x4C
170#define VERSATILE_FLASHCTRL \
171 (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
172/* Enable writing to flash */
173#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0)
wdenkc3919532004-10-11 22:51:13 +0000174
wdenk4989f872004-03-14 15:06:13 +0000175/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200176#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
177#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
178
179/*
180 * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block
181 * i.e.
182 * the bottom "sector" (bottom boot), or top "sector"
183 * (top boot), is a seperate erase region divided into
184 * 4 (equal) smaller sectors. This, notionally, allows
185 * quicker erase/rewrire of the most frequently changed
186 * area......
187 * CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4
188 */
wdenk4989f872004-03-14 15:06:13 +0000189
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200190#ifdef CONFIG_ARCH_VERSATILE_AB
191#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */
192#define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE)
193#define CONFIG_SYS_MAX_FLASH_SECT (520)
194#endif
wdenk4989f872004-03-14 15:06:13 +0000195
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200196#ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */
197#define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
198#define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE
199#define CONFIG_SYS_MAX_FLASH_SECT (260)
200#endif
201
202#define CONFIG_SYS_FLASH_BASE 0x34000000
203#define CONFIG_SYS_MAX_FLASH_BANKS 1
204
205#define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE)
206
207/* The ARM Boot Monitor is shipped in the lowest sector of flash */
208
209#define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200210#define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE)
211#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
212#define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN)
213
214#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
215#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
wdenkc3919532004-10-11 22:51:13 +0000216
402jagan@gmail.com27cd58f2012-07-29 04:26:08 +0000217#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
Stefano Babic491ff7f2011-06-24 03:04:38 +0000218#endif
219
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200220#endif /* __CONFIG_H */