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git01.mediatek.com / filogic / uboot / 5066327ae3d23d1e4011595bd30b80237882e736 / . / board / amcc / redwood / init.S
blob: 748422dedd1729d1abb50d5dd04d5a86bd6989d5 [file] [log] [blame]
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]1/*
2 * (C) Copyright 2008
3 * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]6 */
7
8#include <ppc_asm.tmpl>
9#include <config.h>
Peter Tyser133c0fe2010-04-12 22:28:07 -0500[diff] [blame]10#include <asm/mmu.h>
Stefan Roese3ddce572010-09-20 16:05:31 +0200[diff] [blame]11#include <asm/ppc4xx.h>
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]12
13/**************************************************************************
14 * TLB TABLE
15 *
16 * This table is used by the cpu boot code to setup the initial tlb
17 * entries. Rather than make broad assumptions in the cpu source tree,
18 * this table lets each board set things up however they like.
19 *
20 * Pointer to the table is returned in r1
21 *
22 *************************************************************************/
23
24 .section .bootpg,"ax"
25 .globl tlbtab
26tlbtab:
27 tlbtab_start
28
29 /*
30 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
31 * speed up boot process. It is patched after relocation to enable SA_I
32 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]33 tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]34
35 /*
36 * TLB entries for SDRAM are not needed on this platform.
37 * They are dynamically generated in the SPD DDR(2) detection
38 * routine.
39 */
40
41 /* Although 512 KB, map 256k at a time */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]42 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
43 tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]44
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]45 tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]46
47 /*
48 * Peripheral base
49 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]50 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]51
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]52 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG)
53 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG)
54 tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]55
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]56 tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG)
57 tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]58
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]59 tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG)
60 tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG)
61 tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG)
Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame]62 tlbtab_end