Marek Vasut | 0b16ba5 | 2022-04-12 17:26:01 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2022 Marek Vasut <marex@denx.de> |
| 4 | */ |
| 5 | |
| 6 | #ifndef __IMX8MM_DATA_MODUL_EDM_SBC_H |
| 7 | #define __IMX8MM_DATA_MODUL_EDM_SBC_H |
| 8 | |
| 9 | #include <linux/sizes.h> |
| 10 | #include <linux/stringify.h> |
| 11 | #include <asm/arch/imx-regs.h> |
| 12 | |
Marek Vasut | 0b16ba5 | 2022-04-12 17:26:01 +0200 | [diff] [blame] | 13 | #ifdef CONFIG_SPL_BUILD |
Marek Vasut | 0b16ba5 | 2022-04-12 17:26:01 +0200 | [diff] [blame] | 14 | #define CONFIG_MALLOC_F_ADDR 0x930000 |
| 15 | |
| 16 | /* For RAW image gives a error info not panic */ |
Marek Vasut | 0b16ba5 | 2022-04-12 17:26:01 +0200 | [diff] [blame] | 17 | |
| 18 | #endif |
| 19 | |
| 20 | /* Link Definitions */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 21 | #define CFG_SYS_INIT_RAM_ADDR 0x40000000 |
| 22 | #define CFG_SYS_INIT_RAM_SIZE 0x200000 |
Marek Vasut | 0b16ba5 | 2022-04-12 17:26:01 +0200 | [diff] [blame] | 23 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 24 | #define CFG_SYS_SDRAM_BASE 0x40000000 |
Marek Vasut | 0b16ba5 | 2022-04-12 17:26:01 +0200 | [diff] [blame] | 25 | #define PHYS_SDRAM 0x40000000 |
| 26 | #define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */ |
| 27 | |
Tom Rini | ae17fa3 | 2022-05-11 18:01:06 -0400 | [diff] [blame] | 28 | #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR |
Marek Vasut | 0b16ba5 | 2022-04-12 17:26:01 +0200 | [diff] [blame] | 29 | |
| 30 | /* PHY needs a longer autonegotiation timeout after reset */ |
| 31 | #define PHY_ANEG_TIMEOUT 20000 |
Marek Vasut | 0b16ba5 | 2022-04-12 17:26:01 +0200 | [diff] [blame] | 32 | |
| 33 | /* USDHC */ |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 34 | #define CFG_SYS_FSL_USDHC_NUM 2 |
| 35 | #define CFG_SYS_FSL_ESDHC_ADDR 0 |
Marek Vasut | 0b16ba5 | 2022-04-12 17:26:01 +0200 | [diff] [blame] | 36 | |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 37 | #define CFG_EXTRA_ENV_SETTINGS \ |
Marek Vasut | 0b16ba5 | 2022-04-12 17:26:01 +0200 | [diff] [blame] | 38 | "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ |
| 39 | "bootlimit=3\0" \ |
| 40 | "devtype=mmc\0" \ |
| 41 | "devpart=1\0" \ |
| 42 | /* Give slow devices beyond USB HUB chance to come up. */ \ |
| 43 | "usb_pgood_delay=2000\0" \ |
| 44 | "dfu_alt_info=" \ |
| 45 | /* RAM block at DRAM offset 256..768 MiB */ \ |
| 46 | "ram ram0=ram ram 0x50000000 0x20000000&" \ |
| 47 | /* 16 MiB SPI NOR */ \ |
| 48 | "mtd nor0=sf raw 0x0 0x1000000\0" \ |
| 49 | "dmo_preboot=" \ |
| 50 | "sf probe ; " /* Scan for SPI NOR, needed by DFU */ \ |
Marek Vasut | 0b16ba5 | 2022-04-12 17:26:01 +0200 | [diff] [blame] | 51 | /* Attempt to start USB and Network console */ \ |
| 52 | "run dmo_usb_cdc_acm_start ; " \ |
| 53 | "run dmo_netconsole_start\0" \ |
| 54 | "dmo_update_env=" \ |
| 55 | "setenv dmo_update_env true ; saveenv ; saveenv\0" \ |
| 56 | "dmo_usb_cdc_acm_start=" \ |
| 57 | "if test \"${dmo_usb_cdc_acm_enabled}\" = \"true\" ; then "\ |
| 58 | /* Ungate IMX8MM_CLK_USB1_CTRL_ROOT */ \ |
| 59 | "mw 0x303844d0 3 ; " \ |
| 60 | /* Read USBNC_n_PHY_STATUS BIT(4) VBUS_VLD */ \ |
| 61 | "setexpr.l usbnc_n_phy_status *0x32e4023c \\\\& 0x8 ; " \ |
| 62 | /* If USB OTG has valid VBUS, enable CDC ACM */ \ |
| 63 | "if test \"${usbnc_n_phy_status}\" -eq 8 ; then "\ |
| 64 | "usb start && " \ |
| 65 | "setenv stderr ${stderr},usbacm && " \ |
| 66 | "setenv stdout ${stdout},usbacm && " \ |
| 67 | "setenv stdin ${stdin},usbacm ; " \ |
| 68 | "fi ; " \ |
| 69 | "fi\0" \ |
Marek Vasut | 0b16ba5 | 2022-04-12 17:26:01 +0200 | [diff] [blame] | 70 | "dmo_netconsole_start=" \ |
| 71 | "if test \"${dmo_netconsole_enabled}\" = \"true\" ; then "\ |
| 72 | "setenv autoload false && " \ |
| 73 | "dhcp && " \ |
| 74 | "setenv autoload && " \ |
| 75 | "setenv ncip ${serverip} && " \ |
| 76 | "setenv stderr ${stderr},nc && " \ |
| 77 | "setenv stdout ${stdout},nc && " \ |
| 78 | "setenv stdin ${stdin},nc ; " \ |
| 79 | "fi" |
| 80 | |
| 81 | #endif |