| Matt Porter | bd1fef5 | 2015-05-05 15:00:23 -0400 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2008-2011 |
| 3 | * Graeme Russ, <graeme.russ@gmail.com> |
| 4 | * |
| 5 | * (C) Copyright 2002 |
| 6 | * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> |
| 7 | * |
| 8 | * (C) Copyright 2002 |
| 9 | * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
| 10 | * |
| 11 | * (C) Copyright 2002 |
| 12 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 13 | * Marius Groeger <mgroeger@sysgo.de> |
| 14 | * |
| 15 | * Copyright 2015 ATS Advanced Telematics Systems GmbH |
| 16 | * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> |
| 17 | * |
| 18 | * SPDX-License-Identifier: GPL-2.0+ |
| 19 | */ |
| 20 | |
| 21 | #include <common.h> |
| 22 | #include <command.h> |
| 23 | |
| 24 | DECLARE_GLOBAL_DATA_PTR; |
| 25 | |
| 26 | /* |
| 27 | * ARMv7M does not support ARM instruction mode. However, the |
| 28 | * interworking BLX and BX instructions do encode the ARM/Thumb |
| 29 | * field in bit 0. This means that when executing any Branch |
| 30 | * and eXchange instruction we must set bit 0 to one to guarantee |
| 31 | * that we keep the processor in Thumb instruction mode. From The |
| 32 | * ARMv7-M Instruction Set A4.1.1: |
| 33 | * "ARMv7-M only supports the Thumb instruction execution state, |
| 34 | * therefore the value of address bit [0] must be 1 in interworking |
| 35 | * instructions, otherwise a fault occurs." |
| 36 | */ |
| 37 | unsigned long do_go_exec(ulong (*entry)(int, char * const []), |
| 38 | int argc, char * const argv[]) |
| 39 | { |
| 40 | ulong addr = (ulong)entry | 1; |
| 41 | entry = (void *)addr; |
| 42 | |
| 43 | return entry(argc, argv); |
| 44 | } |