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Priyanka Jainfd45ca02018-11-28 13:04:27 +00001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP LX2160ARDB device tree source
4 *
5 * Author: Priyanka Jain <priyanka.jain@nxp.com>
6 * Sriram Dash <sriram.dash@nxp.com>
7 *
8 * Copyright 2018 NXP
9 *
10 */
11
12/dts-v1/;
13
14#include "fsl-lx2160a.dtsi"
15
16/ {
17 model = "NXP Layerscape LX2160ARDB Board";
18 compatible = "fsl,lx2160ardb", "fsl,lx2160a";
Kuldeep Singh6b614242019-11-06 16:38:01 +053019 aliases {
20 spi0 = &fspi;
21 };
Priyanka Jainfd45ca02018-11-28 13:04:27 +000022};
23
24&esdhc0 {
25 status = "okay";
26};
27
28&esdhc1 {
29 status = "okay";
Yinbo Zhud8a7c222019-07-16 15:09:09 +080030 mmc-hs200-1_8v;
Priyanka Jainfd45ca02018-11-28 13:04:27 +000031};
32
Kuldeep Singh6b614242019-11-06 16:38:01 +053033&fspi {
34 status = "okay";
35
36 mt35xu512aba0: flash@0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "jedec,spi-nor";
40 spi-max-frequency = <50000000>;
41 reg = <0>;
Kuldeep Singh9a3844b2020-03-14 18:23:56 +053042 spi-rx-bus-width = <8>;
43 spi-tx-bus-width = <1>;
Kuldeep Singh6b614242019-11-06 16:38:01 +053044 };
45
46 mt35xu512aba1: flash@1 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "jedec,spi-nor";
50 spi-max-frequency = <50000000>;
51 reg = <1>;
Kuldeep Singh9a3844b2020-03-14 18:23:56 +053052 spi-rx-bus-width = <8>;
53 spi-tx-bus-width = <1>;
Kuldeep Singh6b614242019-11-06 16:38:01 +053054 };
55};
56
Chuanhua Han1a64fb02019-07-10 21:00:26 +080057&i2c0 {
58 status = "okay";
59 u-boot,dm-pre-reloc;
60};
61
Chuanhua Han9312dcb2019-07-10 21:00:25 +080062&i2c4 {
63 status = "okay";
64
65 rtc@51 {
66 compatible = "pcf2127-rtc";
67 reg = <0x51>;
68 };
69};
70
Priyanka Jainfd45ca02018-11-28 13:04:27 +000071&sata0 {
72 status = "okay";
73};
74
75&sata1 {
76 status = "okay";
77};
78
79&sata2 {
80 status = "okay";
81};
82
83&sata3 {
84 status = "okay";
85};