blob: 99406151bf593d41a6ae43bb76f63044a4a07fcb [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glass9d5d1cc2015-08-30 16:55:42 -06002/*
3 * Google Veyron (and derivatives) board device tree source
4 *
5 * Copyright 2014 Google, Inc
Simon Glass9d5d1cc2015-08-30 16:55:42 -06006 */
7
8#include <dt-bindings/clock/rockchip,rk808.h>
9#include <dt-bindings/input/input.h>
10#include "rk3288.dtsi"
11
12/ {
13 memory {
Johan Jonker9a26fb12023-12-27 13:06:47 +010014 reg = <0x0 0x0 0x0 0x80000000>;
Simon Glass9d5d1cc2015-08-30 16:55:42 -060015 };
16
17 chosen {
18 stdout-path = &uart2;
Simon Glass9d5d1cc2015-08-30 16:55:42 -060019 };
20
21 firmware {
22 chromeos {
23 pinctrl-names = "default";
24 pinctrl-0 = <&fw_wp_ap>;
25 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
26 };
27 };
28
29 backlight: backlight {
30 compatible = "pwm-backlight";
31 brightness-levels = <
32 0 1 2 3 4 5 6 7
33 8 9 10 11 12 13 14 15
34 16 17 18 19 20 21 22 23
35 24 25 26 27 28 29 30 31
36 32 33 34 35 36 37 38 39
37 40 41 42 43 44 45 46 47
38 48 49 50 51 52 53 54 55
39 56 57 58 59 60 61 62 63
40 64 65 66 67 68 69 70 71
41 72 73 74 75 76 77 78 79
42 80 81 82 83 84 85 86 87
43 88 89 90 91 92 93 94 95
44 96 97 98 99 100 101 102 103
45 104 105 106 107 108 109 110 111
46 112 113 114 115 116 117 118 119
47 120 121 122 123 124 125 126 127
48 128 129 130 131 132 133 134 135
49 136 137 138 139 140 141 142 143
50 144 145 146 147 148 149 150 151
51 152 153 154 155 156 157 158 159
52 160 161 162 163 164 165 166 167
53 168 169 170 171 172 173 174 175
54 176 177 178 179 180 181 182 183
55 184 185 186 187 188 189 190 191
56 192 193 194 195 196 197 198 199
57 200 201 202 203 204 205 206 207
58 208 209 210 211 212 213 214 215
59 216 217 218 219 220 221 222 223
60 224 225 226 227 228 229 230 231
61 232 233 234 235 236 237 238 239
62 240 241 242 243 244 245 246 247
63 248 249 250 251 252 253 254 255>;
64 default-brightness-level = <128>;
65 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
66 backlight-boot-off;
67 pinctrl-names = "default";
68 pinctrl-0 = <&bl_en>;
69 pwms = <&pwm0 0 1000000 0>;
70 };
71
72 panel: panel {
73 compatible ="cnm,n116bgeea2","simple-panel";
74 status = "okay";
75 power-supply = <&vcc33_lcd>;
76 backlight = <&backlight>;
77 };
78
79 gpio_keys: gpio-keys {
80 compatible = "gpio-keys";
Simon Glass9d5d1cc2015-08-30 16:55:42 -060081
82 pinctrl-names = "default";
83 pinctrl-0 = <&pwr_key_h>;
84 power {
85 label = "Power";
86 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
87 linux,code = <KEY_POWER>;
88 debounce-interval = <100>;
89 gpio-key,wakeup;
90 };
91 };
92
93 gpio-restart {
94 compatible = "gpio-restart";
95 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&ap_warm_reset_h>;
98 priority = /bits/ 8 <200>;
99 };
100
Simon Glassaf0b7442016-01-21 19:43:36 -0700101 emmc_pwrseq: emmc-pwrseq {
102 compatible = "mmc-pwrseq-emmc";
103 pinctrl-0 = <&emmc_reset>;
104 pinctrl-names = "default";
105 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
106 };
107
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600108 sound {
109 compatible = "rockchip,rockchip-audio-max98090";
110 rockchip,model = "ROCKCHIP-I2S";
111 rockchip,i2s-controller = <&i2s>;
112 rockchip,audio-codec = <&max98090>;
113 rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
114 rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
115 rockchip,headset-codec = <&headsetcodec>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&mic_det>, <&hp_det>;
118 };
119
120 vdd_logic: pwm-regulator {
121 compatible = "pwm-regulator";
122 pwms = <&pwm1 0 2000 0>;
123
124 voltage-table = <1350000 0>,
125 <1300000 10>,
126 <1250000 20>,
127 <1200000 31>,
128 <1150000 41>,
129 <1100000 52>,
130 <1050000 62>,
131 <1000000 72>,
132 < 950000 83>;
133
134 regulator-min-microvolt = <950000>;
135 regulator-max-microvolt = <1350000>;
136 regulator-name = "vdd_logic";
137 regulator-ramp-delay = <4000>;
138 };
139
140 vcc33_sys: vcc33-sys {
141 compatible = "regulator-fixed";
142 regulator-name = "vcc33_sys";
143 regulator-always-on;
144 regulator-boot-on;
145 regulator-min-microvolt = <3300000>;
146 regulator-max-microvolt = <3300000>;
147 vin-supply = <&vccsys>;
148 };
149
150 vcc_5v: vcc-5v {
151 compatible = "regulator-fixed";
152 regulator-name = "vcc_5v";
153 regulator-always-on;
154 regulator-boot-on;
155 regulator-min-microvolt = <5000000>;
156 regulator-max-microvolt = <5000000>;
157 };
158
159 vcc50_hdmi: vcc50-hdmi {
160 compatible = "regulator-fixed";
161 regulator-name = "vcc50_hdmi";
162 regulator-always-on;
163 regulator-boot-on;
164 vin-supply = <&vcc_5v>;
165 };
166
167 bt_regulator: bt-regulator {
168 /*
169 * On the module itself this is one of these (depending
170 * on the actual card pouplated):
171 * - BT_I2S_WS_BT_RFDISABLE_L
172 * - No connect
173 */
174
175 compatible = "regulator-fixed";
176 enable-active-high;
177 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&bt_enable_l>;
180 regulator-name = "bt_regulator";
181 };
182
183 wifi_regulator: wifi-regulator {
184 /*
185 * On the module itself this is one of these (depending
186 * on the actual card populated):
187 * - SDIO_RESET_L_WL_REG_ON
188 * - PDN (power down when low)
189 */
190
191 compatible = "regulator-fixed";
192 enable-active-high;
193 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&wifi_enable_h>;
196 regulator-name = "wifi_regulator";
197
198 /* Faux input supply. See bt_regulator description. */
199 vin-supply = <&bt_regulator>;
200 };
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600201};
202
203&cpu0 {
204 cpu0-supply = <&vdd_cpu>;
205};
206
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600207&efuse {
208 status = "okay";
209};
210
211&emmc {
212 broken-cd;
213 bus-width = <8>;
214 cap-mmc-highspeed;
215 mmc-hs200-1_8v;
Simon Glassaf0b7442016-01-21 19:43:36 -0700216 mmc-pwrseq = <&emmc_pwrseq>;
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600217 disable-wp;
218 non-removable;
219 num-slots = <1>;
220 pinctrl-names = "default";
Simon Glassaf0b7442016-01-21 19:43:36 -0700221 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>;
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600222 status = "okay";
223};
224
225&sdio0 {
226 broken-cd;
227 bus-width = <4>;
228 cap-sd-highspeed;
229 sd-uhs-sdr12;
230 sd-uhs-sdr25;
231 sd-uhs-sdr50;
232 sd-uhs-sdr104;
233 cap-sdio-irq;
234 card-external-vcc-supply = <&wifi_regulator>;
235 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
236 <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>;
237 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock";
238 keep-power-in-suspend;
239 non-removable;
240 num-slots = <1>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
243 status = "okay";
244 vmmc-supply = <&vcc33_sys>;
245 vqmmc-supply = <&vcc18_wl>;
246};
247
248&sdmmc {
249 bus-width = <4>;
250 cap-mmc-highspeed;
251 cap-sd-highspeed;
252 sd-uhs-sdr12;
253 sd-uhs-sdr25;
254 sd-uhs-sdr50;
255 sd-uhs-sdr104;
256 card-detect-delay = <200>;
257 cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
258 num-slots = <1>;
259 status = "okay";
260 vmmc-supply = <&vcc33_sd>;
261 vqmmc-supply = <&vccio_sd>;
262};
263
264&spi2 {
265 status = "okay";
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600266
267 spi_flash: spiflash@0 {
Neil Armstronga009fa72019-02-10 10:16:20 +0000268 compatible = "spidev", "jedec,spi-nor";
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600269 spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
270 reg = <0>;
271 };
272};
273
274&i2c0 {
275 status = "okay";
276
277 clock-frequency = <400000>;
278 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
279 i2c-scl-rising-time-ns = <100>; /* 45ns measured */
280
281 rk808: pmic@1b {
282 compatible = "rockchip,rk808";
283 clock-output-names = "xin32k", "wifibt_32kin";
284 interrupt-parent = <&gpio0>;
285 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&pmic_int_l>;
288 reg = <0x1b>;
289 rockchip,system-power-controller;
290 wakeup-source;
291 #clock-cells = <1>;
292
293 vcc1-supply = <&vcc33_sys>;
294 vcc2-supply = <&vcc33_sys>;
295 vcc3-supply = <&vcc33_sys>;
296 vcc4-supply = <&vcc33_sys>;
297 vcc6-supply = <&vcc_5v>;
298 vcc7-supply = <&vcc33_sys>;
299 vcc8-supply = <&vcc33_sys>;
300 vcc9-supply = <&vcc_5v>;
301 vcc10-supply = <&vcc33_sys>;
302 vcc11-supply = <&vcc_5v>;
303 vcc12-supply = <&vcc_18>;
304
305 vddio-supply = <&vcc33_io>;
306
307 regulators {
308 vdd_cpu: DCDC_REG1 {
309 regulator-always-on;
310 regulator-boot-on;
311 regulator-min-microvolt = <750000>;
312 regulator-max-microvolt = <1450000>;
313 regulator-name = "vdd_arm";
314 regulator-ramp-delay = <6001>;
315 regulator-suspend-mem-disabled;
316 };
317
318 vdd_gpu: DCDC_REG2 {
319 regulator-always-on;
320 regulator-boot-on;
321 regulator-min-microvolt = <800000>;
322 regulator-max-microvolt = <1250000>;
323 regulator-name = "vdd_gpu";
324 regulator-ramp-delay = <6001>;
325 regulator-suspend-mem-disabled;
326 };
327
328 vcc135_ddr: DCDC_REG3 {
329 regulator-always-on;
330 regulator-boot-on;
331 regulator-name = "vcc135_ddr";
332 regulator-suspend-mem-enabled;
333 };
334
335 /*
336 * vcc_18 has several aliases. (vcc18_flashio and
337 * vcc18_wl). We'll add those aliases here just to
338 * make it easier to follow the schematic. The signals
339 * are actually hooked together and only separated for
340 * power measurement purposes).
341 */
342 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
343 regulator-always-on;
344 regulator-boot-on;
345 regulator-min-microvolt = <1800000>;
346 regulator-max-microvolt = <1800000>;
347 regulator-name = "vcc_18";
348 regulator-suspend-mem-microvolt = <1800000>;
349 };
350
351 /*
352 * Note that both vcc33_io and vcc33_pmuio are always
353 * powered together. To simplify the logic in the dts
354 * we just refer to vcc33_io every time something is
355 * powered from vcc33_pmuio. In fact, on later boards
356 * (such as danger) they're the same net.
357 */
358 vcc33_io: LDO_REG1 {
359 regulator-always-on;
360 regulator-boot-on;
361 regulator-min-microvolt = <3300000>;
362 regulator-max-microvolt = <3300000>;
363 regulator-name = "vcc33_io";
364 regulator-suspend-mem-microvolt = <3300000>;
365 };
366
367 vdd_10: LDO_REG3 {
368 regulator-always-on;
369 regulator-boot-on;
370 regulator-min-microvolt = <1000000>;
371 regulator-max-microvolt = <1000000>;
372 regulator-name = "vdd_10";
373 regulator-suspend-mem-microvolt = <1000000>;
374 };
375
376 vccio_sd: LDO_REG4 {
377 regulator-min-microvolt = <1800000>;
378 regulator-max-microvolt = <3300000>;
379 regulator-name = "vccio_sd";
380 regulator-suspend-mem-disabled;
381 };
382
383 vcc33_sd: LDO_REG5 {
384 regulator-min-microvolt = <3300000>;
385 regulator-max-microvolt = <3300000>;
386 regulator-name = "vcc33_sd";
387 regulator-suspend-mem-disabled;
388 };
389
390 vcc18_codec: LDO_REG6 {
391 regulator-always-on;
392 regulator-boot-on;
393 regulator-min-microvolt = <1800000>;
394 regulator-max-microvolt = <1800000>;
395 regulator-name = "vcc18_codec";
396 regulator-suspend-mem-disabled;
397 };
398
399 vdd10_lcd_pwren_h: LDO_REG7 {
400 regulator-always-on;
401 regulator-boot-on;
402 regulator-min-microvolt = <2500000>;
403 regulator-max-microvolt = <2500000>;
404 regulator-name = "vdd10_lcd_pwren_h";
405 regulator-suspend-mem-disabled;
406 };
407
408 vcc33_lcd: SWITCH_REG1 {
409 regulator-always-on;
410 regulator-boot-on;
411 regulator-name = "vcc33_lcd";
412 regulator-suspend-mem-disabled;
413 };
414 };
415 };
416};
417
418&i2c1 {
419 status = "okay";
420
421 clock-frequency = <400000>;
422 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
423 i2c-scl-rising-time-ns = <100>; /* 40ns measured */
424
425 tpm: tpm@20 {
426 compatible = "infineon,slb9645tt";
427 reg = <0x20>;
428 powered-while-suspended;
429 };
430};
431
432&i2c2 {
433 status = "okay";
434
435 /* 100kHz since 4.7k resistors don't rise fast enough */
436 clock-frequency = <100000>;
437 i2c-scl-falling-time-ns = <50>; /* 10ns measured */
438 i2c-scl-rising-time-ns = <800>; /* 600ns measured */
439
440 max98090: max98090@10 {
441 compatible = "maxim,max98090";
442 reg = <0x10>;
Simon Glassb7e0e852018-12-27 20:15:23 -0700443 #sound-dai-cells = <0>;
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600444 interrupt-parent = <&gpio6>;
445 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
446 pinctrl-names = "default";
447 pinctrl-0 = <&int_codec>;
448 };
449};
450
451&i2c3 {
452 status = "okay";
453
454 clock-frequency = <400000>;
455 i2c-scl-falling-time-ns = <50>;
456 i2c-scl-rising-time-ns = <300>;
457};
458
459&i2c4 {
460 status = "okay";
461
462 clock-frequency = <400000>;
463 i2c-scl-falling-time-ns = <50>; /* 11ns measured */
464 i2c-scl-rising-time-ns = <300>; /* 225ns measured */
465
466 headsetcodec: ts3a227e@3b {
467 compatible = "ti,ts3a227e";
468 reg = <0x3b>;
469 interrupt-parent = <&gpio0>;
470 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&ts3a227e_int_l>;
473 ti,micbias = <7>; /* MICBIAS = 2.8V */
474 };
475};
476
477&i2c5 {
478 status = "okay";
479
480 clock-frequency = <100000>;
481 i2c-scl-falling-time-ns = <300>;
482 i2c-scl-rising-time-ns = <1000>;
483};
484
485&i2s {
486 status = "okay";
487 clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
488 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
489};
490
Johan Jonkera5b4bdb2023-03-15 19:31:57 +0100491&io_domains {
492 audio-supply = <&vcc18_codec>;
493 bb-supply = <&vcc33_io>;
494 dvp-supply = <&vcc_18>;
495 flash0-supply = <&vcc18_flashio>;
496 gpio1830-supply = <&vcc33_io>;
497 gpio30-supply = <&vcc33_io>;
498 lcdc-supply = <&vcc33_lcd>;
499 sdcard-supply = <&vccio_sd>;
500 wifi-supply = <&vcc18_wl>;
501 status = "okay";
502};
503
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600504&wdt {
505 status = "okay";
506};
507
508&pwm0 {
509 status = "okay";
510};
511
512&pwm1 {
513 status = "okay";
514};
515
516&uart0 {
517 status = "okay";
518
519 /* Pins don't include flow control by default; add that in */
520 pinctrl-names = "default";
521 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
522 /* We need to go faster than 24MHz, so adjust clock parents / rates */
523 assigned-clocks = <&cru SCLK_UART0>;
524 assigned-clock-rates = <48000000>;
525};
526
527&uart1 {
528 status = "okay";
529};
530
531&uart2 {
532 status = "okay";
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600533 reg-shift = <2>;
534};
535
536&vopb {
537 status = "okay";
538};
539
540&vopb_mmu {
541 status = "okay";
542};
543
544&vopl {
545 status = "okay";
546};
547
548&vopl_mmu {
549 status = "okay";
550};
551
552&edp {
553 status = "okay";
554 rockchip,panel = <&panel>;
555};
556
557&hdmi {
558 status = "okay";
559};
560
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600561&gpu {
562 status = "okay";
563};
564
565&tsadc {
566 tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
567 tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
568 status = "okay";
569};
570
571&pinctrl {
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600572 pinctrl-names = "default", "sleep";
573 pinctrl-0 = <
574 /* Common for sleep and wake, but no owners */
575 &ddr0_retention
576 &ddrio_pwroff
577 &global_pwroff
578
579 /* Wake only */
580 &bt_dev_wake_awake
581 >;
582 pinctrl-1 = <
583 /* Common for sleep and wake, but no owners */
584 &ddr0_retention
585 &ddrio_pwroff
586 &global_pwroff
587
588 /* Sleep only */
589 &bt_dev_wake_sleep
590 >;
591
592 /* Add this for sdmmc pins to SD card */
593 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
594 drive-strength = <8>;
595 };
596
597 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
598 bias-pull-up;
599 drive-strength = <8>;
600 };
601
602 pcfg_output_high: pcfg-output-high {
603 output-high;
604 };
605
606 pcfg_output_low: pcfg-output-low {
607 output-low;
608 };
609
610 backlight {
611 bl_en: bl-en {
612 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
613 };
614 };
615
616 buttons {
617 pwr_key_h: pwr-key-h {
618 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
619 };
620 };
621
622 codec {
623 hp_det: hp-det {
624 rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
625 };
626 int_codec: int-codec {
627 rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>;
628 };
629 mic_det: mic-det {
630 rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
631 };
632 };
633
634 emmc {
Simon Glassaf0b7442016-01-21 19:43:36 -0700635 emmc_reset: emmc-reset {
636 rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600637 };
638
639 /*
640 * We run eMMC at max speed; bump up drive strength.
641 * We also have external pulls, so disable the internal ones.
642 */
643 emmc_clk: emmc-clk {
644 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
645 };
646
647 emmc_cmd: emmc-cmd {
648 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
649 };
650
651 emmc_bus8: emmc-bus8 {
652 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
653 <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
654 <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
655 <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
656 <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
657 <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
658 <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
659 <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
660 };
661 };
662
663 headset {
664 ts3a227e_int_l: ts3a227e-int-l {
665 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
666 };
667 };
668
669 pmic {
670 pmic_int_l: pmic-int-l {
Simon Glass930ec982016-01-21 19:43:37 -0700671 /*
672 * Causes jerry to hang when probing bus 0
673 * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
674 */
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600675 };
676 };
677
678 reboot {
679 ap_warm_reset_h: ap-warm-reset-h {
680 rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
681 };
682 };
683
684 sdio0 {
685 wifi_enable_h: wifienable-h {
686 rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
687 };
688
689 /* NOTE: mislabelled on schematic; should be bt_enable_h */
690 bt_enable_l: bt-enable-l {
691 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
692 };
693
694 /*
695 * We run sdio0 at max speed; bump up drive strength.
696 * We also have external pulls, so disable the internal ones.
697 */
698 sdio0_bus4: sdio0-bus4 {
699 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
700 <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
701 <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
702 <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
703 };
704
705 sdio0_cmd: sdio0-cmd {
706 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
707 };
708
709 sdio0_clk: sdio0-clk {
710 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
711 };
712
713 /*
714 * These pins are only present on very new veyron boards; on
715 * older boards bt_dev_wake is simply always high. Note that
716 * gpio4_26 is a NC on old veyron boards, so it doesn't hurt
717 * to map this pin everywhere
718 */
719 bt_dev_wake_sleep: bt-dev-wake-sleep {
720 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>;
721 };
722
723 bt_dev_wake_awake: bt-dev-wake-awake {
724 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>;
725 };
726 };
727
728 sdmmc {
729 /*
730 * We run sdmmc at max speed; bump up drive strength.
731 * We also have external pulls, so disable the internal ones.
732 */
733 sdmmc_bus4: sdmmc-bus4 {
734 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
735 <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
736 <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
737 <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
738 };
739
740 sdmmc_clk: sdmmc-clk {
741 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
742 };
743
744 sdmmc_cmd: sdmmc-cmd {
745 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
746 };
747
748 /*
749 * Builtin CD line is hooked to ground to prevent JTAG at boot
750 * (and also to get the voltage rail correct). Make we
751 * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
752 * think there's a card inserted
753 */
754 sdmmc_cd_disabled: sdmmc-cd-disabled {
755 rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
756 };
757
758 /* This is where we actually hook up CD */
759 sdmmc_cd_gpio: sdmmc-cd-gpio {
760 rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
761 };
762 };
763
764 tpm {
765 tpm_int_h: tpm-int-h {
766 rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
767 };
768 };
769
770 write-protect {
771 fw_wp_ap: fw-wp-ap {
772 rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
773 };
774 };
775};
776
777&usbphy {
778 status = "okay";
779};
780
781&usb_host0_ehci {
782 status = "okay";
783 needs-reset-on-resume;
784};
785
786&usb_host1 {
787 status = "okay";
788};
789
790&usb_otg {
791 dr_mode = "host";
792 status = "okay";
793 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
794 assigned-clock-parents = <&cru SCLK_OTGPHY0>;
795};