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Tom Rinidec7ea02024-05-20 13:35:03 -06001# SPDX-License-Identifier: GPL-2.0-or-later
2#
3# (C) Copyright 2022 - Analog Devices, Inc.
4#
5# Written and/or maintained by Timesys Corporation
6#
7# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
8# Contact: Greg Malysa <greg.malysa@timesys.com>
9#
10
11# All 32-bit platforms require SYS_ARM_CACHE_WRITETHROUGH
12# But it is ignored if selected here, so it must be in the defconfig
13
14if ARCH_SC5XX
15
Oliver Gaskelld4f7cb52024-09-12 16:50:54 +010016config SYS_VENDOR
17 default "adi"
18
Oliver Gaskell3fe227b2024-09-12 16:50:53 +010019choice
20 prompt "SC5xx SoC Select"
21 help
22 Selects which series of Analog Devices SC5xx chips to support.
23
Tom Rinidec7ea02024-05-20 13:35:03 -060024config SC57X
Oliver Gaskell3fe227b2024-09-12 16:50:53 +010025 bool "SC57x series"
Tom Rinidec7ea02024-05-20 13:35:03 -060026 select COMMON_CLK_ADI_SC57X
Oliver Gaskell3fe227b2024-09-12 16:50:53 +010027 select CPU_V7A
Tom Rinidec7ea02024-05-20 13:35:03 -060028
29config SC58X
Oliver Gaskell3fe227b2024-09-12 16:50:53 +010030 bool "SC58x series"
Tom Rinidec7ea02024-05-20 13:35:03 -060031 select COMMON_CLK_ADI_SC58X
Oliver Gaskell3fe227b2024-09-12 16:50:53 +010032 select CPU_V7A
Tom Rinidec7ea02024-05-20 13:35:03 -060033
34config SC59X
Oliver Gaskell3fe227b2024-09-12 16:50:53 +010035 bool "SC59x 32-bit series"
Tom Rinidec7ea02024-05-20 13:35:03 -060036 select COMMON_CLK_ADI_SC594
Oliver Gaskell3fe227b2024-09-12 16:50:53 +010037 select CPU_V7A
Oliver Gaskell14032b32024-09-12 16:50:56 +010038 select NOP_PHY if PHY
Tom Rinidec7ea02024-05-20 13:35:03 -060039
40config SC59X_64
Oliver Gaskell3fe227b2024-09-12 16:50:53 +010041 bool "SC59x 64-bit series"
Tom Rinidec7ea02024-05-20 13:35:03 -060042 select ARM64
Tom Rinidec7ea02024-05-20 13:35:03 -060043 select COMMON_CLK_ADI_SC598
44 select GICV3
Oliver Gaskelld4f7cb52024-09-12 16:50:54 +010045 select GICV3_SUPPORT_GIC600
Tom Rinidec7ea02024-05-20 13:35:03 -060046 select GIC_600_CLEAR_RDPD
Oliver Gaskell3fe227b2024-09-12 16:50:53 +010047 select MMC_SDHCI_ADMA_FORCE_32BIT
Oliver Gaskelld4f7cb52024-09-12 16:50:54 +010048 select NOP_PHY if PHY
49
50endchoice
51
Oliver Gaskell14032b32024-09-12 16:50:56 +010052if SC59X
53
54choice
55 prompt "SC59x 32-bit board select"
56
57config TARGET_SC594_SOM_EZKIT
58 bool
59 prompt "SC594-SOM with SOMCRR-EZKIT"
60 select ADI_CARRIER_SOMCRR_EZKIT
61
62endchoice
63
64endif
65
Oliver Gaskelld4f7cb52024-09-12 16:50:54 +010066if SC59X_64
67
68choice
69 prompt "SC59x 64-bit board select"
70
Oliver Gaskellc69c7f82024-09-12 16:50:55 +010071config TARGET_SC598_SOM_EZLITE
72 bool
73 prompt "SC598-SOM with SOMCRR-EZLITE"
74 select ADI_CARRIER_SOMCRR_EZLITE
75
Oliver Gaskelld4f7cb52024-09-12 16:50:54 +010076config TARGET_SC598_SOM_EZKIT
77 bool
78 prompt "SC598-SOM with SOMCRR-EZKIT"
79 select ADI_CARRIER_SOMCRR_EZKIT
Tom Rinidec7ea02024-05-20 13:35:03 -060080
Oliver Gaskell3fe227b2024-09-12 16:50:53 +010081endchoice
82
Oliver Gaskelld4f7cb52024-09-12 16:50:54 +010083endif
84
85config ADI_IMAGE
86 string "ADI fitImage type"
87 help
88 The image built by the ADI ADSP Linux build system.
89 Is one of tiny, minimal, full.
90
Tom Rinidec7ea02024-05-20 13:35:03 -060091config SC_BOOT_MODE
92 int "SC5XX boot mode select"
93 default 1
94 range 0 7
95 help
96 Mode 0: do nothing, just idle
97 Mode 1: boot ldr out of serial flash
98 Mode 7: boot ldr over uart
99
100config SC_BOOT_SPI_BUS
101 int "sc5xx spi boot bus"
102 default 2
103 range 0 4
104 help
105 This is the SPI peripheral number to use for booting, X in the
106 expression `sf probe X:Y`
107
108config SC_BOOT_SPI_SSEL
109 int "sc5xx spi boot chipselect"
110 default 1
111 range 0 6
112 help
113 This is the SPI chip select number to use for booting, Y in the
114 expression `sf probe X:Y`
115
116config SC_BOOT_OSPI_BUS
117 int "sc5xx ospi boot bus"
118 default 0
119 help
120 This is the OSPI peripheral number to use for booting, X in the
121 expression `sf probe X:Y`
122
123config SC_BOOT_OSPI_SSEL
124 int "sc5xx ospi boot chipselect"
125 default 0
126 help
127 This is the OSPI chip select number to use for booting, Y in the
128 expression `sf probe X:Y`
129
Oliver Gaskelld4f7cb52024-09-12 16:50:54 +0100130config SYS_BOOTM_LEN
131 hex
132 default 0x1800000
133
Tom Rinidec7ea02024-05-20 13:35:03 -0600134config SYS_FLASH_BASE
135 hex
136 default 0x60000000
137
Oliver Gaskelld4f7cb52024-09-12 16:50:54 +0100138config SYS_MALLOC_F_LEN
139 default 0x14000
140
141config SYS_LOAD_ADDR
142 hex
143 default 0x0
144
145config SYS_MALLOC_LEN
146 hex
147 default 1048576
148
Tom Rinidec7ea02024-05-20 13:35:03 -0600149config UART_CONSOLE
150 int
151 default 0
152
153config UART4_SERIAL
154 bool
155 depends on DM_SERIAL
156 default y
157
158config WDT_ADI
159 bool
160 default y
161
162config WATCHDOG_TIMEOUT_MSECS
163 int
164 default 30000
165
166config DW_PORTS
167 int
168 default 1
169
170config ADI_BUG_EZKHW21
171 bool "SC584 EZKIT phy bug workaround"
172 depends on SC58X
173 help
174 This workaround affects the SC584 EZKIT and addresses bug EZKHW21.
175 It disables gigabit ethernet mode and limits the board to 100 Mbps
176
177config ADI_CARRIER_SOMCRR_EZKIT
178 bool "Support the EV-SOMCRR-EZKIT"
179 depends on (SC59X || SC59X_64)
180 help
181 Say y to include support for the EV-SOMCRR-EZKIT carrier board,
182 which is compatible with the SC594 and SC598 SOMs. The EZKIT is
183 mutually incompatible with the EZLITE.
184
185config ADI_CARRIER_SOMCRR_EZLITE
186 bool "Support the EV-SOMCRR-EZLITE"
187 depends on (SC59X || SC59X_64)
188 help
189 Say y to include support for the EV-SOMCRR-EZLITE carrier board,
190 which is compatible with the SC594 and SC598 SOMs. The EZLITE is
191 mutually incompatible with the EZKIT.
192
193config ADI_SPL_FORCE_BMODE
194 int "Force the SPL to use this BMODE device during next boot stage"
195 default 0
196 range 0 9
197 depends on SPL
198 help
199 Force the SPL to use this BMODE device during next boot stage.
200 For example, if booting via QSPI, we can force the second stage
201 Of the boot process to use other peripherals via:
202 1 = QSPI -> QSPI
203 5 = QSPI -> OSPI
204 6 = QSPI -> eMMC
205
206config ADI_USE_DMC0
207 bool "Configure DMC0"
208 default y
209 help
210 During hardware initialization, channel 0 of the DMC will be
211 initialized. Select this if you have DMC0 connected to external
212 DDR memory. This is expected to be true for every board using
213 an SC5xx SoC.
214
215config ADI_USE_DMC1
216 bool "Configure DMC1"
217 help
218 During hardware initialization, channel 1 of the DMC will be
219 initialized. Not all processors have a DMC1. Select this if your
220 SoC has DMC1 and you have it connected to external DDR memory.
221
222config ADI_USE_DDR2
223 bool "Configure DMC for DDR2 mode"
224 help
225 Configure the DMC in DDR2 mode. The default is DDR3 and not all
226 parts may actually support DDR2. Please consult the manual for
227 the SoC that you are using to determine if DDR2 mode is supported.
228 This also requires that DDR2 memory is present on the board or it
229 will probably cause strange failure.
230
231menu "Clock configuration"
232
233config CGU0_DF_DIV
234 int "CGU0_DF_DIV"
235 range 0 1
236 help
237 Select 0 to pass CLKIN to PLL
238 Select 1 to pass CLKIN/2 to PLL
239
240config CGU0_VCO_MULT
241 int "CGU0_VCO_MULT"
242 range 0 127
243 help
244 VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL
245 A value of 0 means 128
246
247config CGU0_CCLK_DIV
248 int "CGU0_CCLK_DIV"
249 range 0 31
250 help
251 CCLK_DIV controls the core clock divider
252 A value of 0 means 32
253 CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV
254
255config CGU0_SCLK_DIV
256 int "CGU0_SCLK_DIV"
257 range 0 31
258 help
259 SCLK_DIV controls the system clock divider
260 A value of 0 means 32
261 SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV
262
263config CGU0_SCLK0_DIV
264 int "CGU0_SCLK0_DIV"
265 range 0 7
266 help
267 A value of 0 means 8
268 SCLK0 = SCLK / SCLK0_DIV
269
270config CGU0_SCLK1_DIV
271 int "CGU0_SCLK1_DIV"
272 depends on (SC57X || SC58X)
273 range 0 7
274 help
275 A value of 0 means 8
276 SCLK1 = SCLK / SCLK1_DIV
277
278config CGU0_DCLK_DIV
279 int "CGU0_DCLK_DIV"
280 range 0 31
281 help
282 DCLK_DIV controls the DDR clock divider
283 A value of 0 means 32
284 DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV
285
286config CGU0_OCLK_DIV
287 int "CGU0_OCLK_DIV"
288 range 0 127
289 help
290 OCLK_DIV controls the output clock divider
291 A value of 0 means 128
292 OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV
293
294config CGU0_DIV_S1SELEX
295 int "CGU0_DIV_S1SELEX"
296 depends on !SC57X && !SC58X
297 range 0 255
298 help
299 CGU0 SCLK1 Extended divisor register.
300 A value of 0 means 256.
301 SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX
302
303config CGU0_CLKOUTSEL
304 int "CGU0_CLKOUTSEL"
305 default 0
306 range 0 31
307 help
308 Select signal driven through CLKOUT pin multiplexer.
309 This value varies on each SOC. Refer to
310 CGU_CLKOUTSEL.CLKOUTSEL in the Hardware Reference Manual
311 for values applicable to each SOC.
312 Commonly, values 0 and 1 select CLKIN0 or CLKIN1 respectively.
313
314config CGU1_PLL3_DDRCLK
315 bool "DDRCLK From 3rd PLL"
316 depends on SC59X_64
317 help
318 3rd PLL output is connected to DMC block when set.
319 When cleared, DDR clock is CLKO3 output of CDU.
320
321config CGU1_PLL3_VCO_MSEL
322 int "CGU0_PLL3_VCO_MSEL"
323 depends on CGU1_PLL3_DDRCLK
324 range 1 128
325 help
326 PLL multiplier value for the 3rd PLL.
327 DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV
328
329config CGU1_PLL3_DCLK_DIV
330 int "CGU0_PLL3_DCLK_DIV"
331 depends on CGU1_PLL3_DDRCLK
332 range 1 32
333 help
334 PLL divider value for the 3rd PLL.
335 DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV
336
337config CGU1_DF_DIV
338 int "CGU1_DF_DIV"
339 range 0 1
340 help
341 Select 0 to pass CLKIN to PLL
342 Select 1 to pass CLKIN/2 to PLL
343
344config CGU1_VCO_MULT
345 int "CGU1_VCO_MULT"
346 range 0 127
347 help
348 VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL
349 A value of 0 means 128
350
351config CGU1_CCLK_DIV
352 int "CGU1_CCLK_DIV"
353 range 0 31
354 help
355 CCLK_DIV controls the core clock divider
356 A value of 0 means 32
357 CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV
358
359config CGU1_SCLK_DIV
360 int "CGU1_SCLK_DIV"
361 range 0 31
362 help
363 SCLK_DIV controls the system clock divider
364 A value of 0 means 32
365 SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV
366
367config CGU1_SCLK0_DIV
368 int "CGU1_SCLK0_DIV"
369 depends on (SC57X || SC58X || SC59X)
370 range 0 7
371 help
372 A value of 0 means 8
373 SCLK0 = SCLK / SCLK0_DIV
374
375config CGU1_SCLK1_DIV
376 int "CGU1_SCLK1_DIV"
377 depends on (SC57X || SC58X)
378 range 0 7
379 help
380 A value of 0 means 8
381 SCLK1 = SCLK / SCLK1_DIV
382
383config CGU1_DCLK_DIV
384 int "CGU1_DCLK_DIV"
385 range 0 31
386 help
387 DCLK_DIV controls the DDR clock divider
388 A value of 0 means 32
389 DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV
390
391config CGU1_OCLK_DIV
392 int "CGU1_OCLK_DIV"
393 range 0 127
394 help
395 OCLK_DIV controls the output clock divider
396 A value of 0 means 128
397 OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV
398
399config CGU1_DIV_S0SELEX
400 int "CGU1_DIV_S0SELEX"
401 depends on !SC57X && !SC58X && !SC59X
402 range 0 255
403 help
404 CGU1 SCLK0 Extended divisor register.
405 A value of 0 means 256.
406 SCLK0 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S0SELEX
407
408config CGU1_DIV_S1SELEX
409 int "CGU1_DIV_S1SELEX"
410 depends on !SC57X && !SC58X
411 range 0 255
412 help
413 CGU1 SCLK1 Extended divisor register.
414 A value of 0 means 256.
415 SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX
416
417config CDU0_CGU1_CLKIN
418 int "CDU0 CGU1 CLKINn Select"
419 default 0
420 range 0 1
421 help
422 Selects source clock for CGU1.
423 0 for CLKIN0
424 1 for CLKIN1
425
426config CDU0_CLKO0
427 int "CDU0_CLKO0"
428 range 1 7
429 help
430 Clock source select. Refer to SOC Hardware Reference Manual
431
432config CDU0_CLKO1
433 int "CDU0_CLKO1"
434 range 1 7
435 help
436 Clock source select. Refer to SOC Hardware Reference Manual
437
438config CDU0_CLKO2
439 int "CDU0_CLKO2"
440 range 1 7
441 help
442 Clock source select. Refer to SOC Hardware Reference Manual
443
444config CDU0_CLKO3
445 int "CDU0_CLKO3"
446 range 1 7
447 help
448 Clock source select. Refer to SOC Hardware Reference Manual
449
450config CDU0_CLKO4
451 int "CDU0_CLKO4"
452 range 1 7
453 help
454 Clock source select. Refer to SOC Hardware Reference Manual
455
456config CDU0_CLKO5
457 int "CDU0_CLKO5"
458 range 1 7
459 help
460 Clock source select. Refer to SOC Hardware Reference Manual
461
462config CDU0_CLKO6
463 int "CDU0_CLKO6"
464 range 1 7
465 help
466 Clock source select. Refer to SOC Hardware Reference Manual
467
468config CDU0_CLKO7
469 int "CDU0_CLKO7"
470 range 1 7
471 help
472 Clock source select. Refer to SOC Hardware Reference Manual
473
474config CDU0_CLKO8
475 int "CDU0_CLKO8"
476 range 1 7
477 help
478 Clock source select. Refer to SOC Hardware Reference Manual
479
480config CDU0_CLKO9
481 int "CDU0_CLKO9"
482 range 1 7
483 help
484 Clock source select. Refer to SOC Hardware Reference Manual
485
486config CDU0_CLKO10
487 int "CDU0_CLKO10"
488 range 1 7
489 depends on (SC59X || SC59X_64)
490 help
491 Clock source select. Refer to SOC Hardware Reference Manual
492
493config CDU0_CLKO12
494 int "CDU0_CLKO12"
495 range 1 7
496 depends on (SC59X || SC59X_64)
497 help
498 Clock source select. Refer to SOC Hardware Reference Manual
499
500config CDU0_CLKO13
501 int "CDU0_CLKO13"
502 range 1 7
503 depends on SC59X_64
504 help
505 Clock source select. Refer to SOC Hardware Reference Manual
506
507config CDU0_CLKO14
508 int "CDU0_CLKO14"
509 range 1 7
510 depends on SC59X_64
511 help
512 Clock source select. Refer to SOC Hardware Reference Manual
513
514endmenu
515
516config ADI_GPIO
517 bool
518 default y
519
520config PINCTRL_ADI
521 bool
522 default y
523
Oliver Gaskelld4f7cb52024-09-12 16:50:54 +0100524source "board/adi/sc598-som-ezkit/Kconfig"
Oliver Gaskellc69c7f82024-09-12 16:50:55 +0100525source "board/adi/sc598-som-ezlite/Kconfig"
Oliver Gaskell14032b32024-09-12 16:50:56 +0100526source "board/adi/sc594-som-ezkit/Kconfig"
Oliver Gaskelld4f7cb52024-09-12 16:50:54 +0100527
Tom Rinidec7ea02024-05-20 13:35:03 -0600528endif