wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 1 | /* |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 2 | * (C) Copyright 2000-2004 |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #include <common.h> |
| 26 | #include <mpc8xx.h> |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 27 | #include "../common/kup.h" |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 28 | #ifdef CONFIG_KUP4K_LOGO |
| 29 | #include "s1d13706.h" |
| 30 | #endif |
| 31 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 32 | DECLARE_GLOBAL_DATA_PTR; |
| 33 | |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 34 | #undef DEBUG |
| 35 | #ifdef DEBUG |
| 36 | # define debugk(fmt,args...) printf(fmt ,##args) |
| 37 | #else |
| 38 | # define debugk(fmt,args...) |
| 39 | #endif |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 40 | |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 41 | typedef struct { |
| 42 | volatile unsigned char *VmemAddr; |
| 43 | volatile unsigned char *RegAddr; |
| 44 | } FB_INFO_S1D13xxx; |
| 45 | |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 46 | |
| 47 | /* ------------------------------------------------------------------------- */ |
| 48 | |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 49 | #ifdef CONFIG_KUP4K_LOGO |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 50 | void lcd_logo(bd_t *bd); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 51 | #endif |
| 52 | |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 53 | |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 54 | /* ------------------------------------------------------------------------- */ |
| 55 | |
| 56 | #define _NOT_USED_ 0xFFFFFFFF |
| 57 | |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 58 | const uint sdram_table[] = { |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 59 | /* |
| 60 | * Single Read. (Offset 0 in UPMA RAM) |
| 61 | */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 62 | 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 63 | 0x1FF77C47, /* last */ |
| 64 | |
| 65 | /* |
| 66 | * SDRAM Initialization (offset 5 in UPMA RAM) |
| 67 | * |
| 68 | * This is no UPM entry point. The following definition uses |
| 69 | * the remaining space to establish an initialization |
| 70 | * sequence, which is executed by a RUN command. |
| 71 | * |
| 72 | */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 73 | 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 74 | |
| 75 | /* |
| 76 | * Burst Read. (Offset 8 in UPMA RAM) |
| 77 | */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 78 | 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, |
| 79 | 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 80 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 81 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 82 | |
| 83 | /* |
| 84 | * Single Write. (Offset 18 in UPMA RAM) |
| 85 | */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 86 | 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 87 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 88 | |
| 89 | /* |
| 90 | * Burst Write. (Offset 20 in UPMA RAM) |
| 91 | */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 92 | 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, |
| 93 | 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ |
| 94 | _NOT_USED_, |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 95 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 96 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 97 | |
| 98 | /* |
| 99 | * Refresh (Offset 30 in UPMA RAM) |
| 100 | */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 101 | 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
| 102 | 0xFFFFFC84, 0xFFFFFC07, /* last */ |
| 103 | _NOT_USED_, _NOT_USED_, |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 104 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 105 | |
| 106 | /* |
| 107 | * Exception. (Offset 3c in UPMA RAM) |
| 108 | */ |
| 109 | 0x7FFFFC07, /* last */ |
| 110 | _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 111 | }; |
| 112 | |
| 113 | /* ------------------------------------------------------------------------- */ |
| 114 | |
| 115 | |
| 116 | /* |
| 117 | * Check Board Identity: |
| 118 | */ |
| 119 | |
| 120 | int checkboard (void) |
| 121 | { |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 122 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
| 123 | uchar *latch,rev,mod; |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 124 | |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 125 | /* |
| 126 | * Init ChipSelect #4 (CAN + HW-Latch) |
| 127 | */ |
| 128 | immap->im_memctl.memc_or4 = 0xFFFF8926; |
| 129 | immap->im_memctl.memc_br4 = 0x90000401; |
wdenk | e07ec1b | 2004-05-12 22:54:36 +0000 | [diff] [blame] | 130 | __asm__ ("eieio"); |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 131 | latch=(uchar *)0x90000200; |
| 132 | rev = (*latch & 0xF8) >> 3; |
| 133 | mod=(*latch & 0x03); |
wdenk | e07ec1b | 2004-05-12 22:54:36 +0000 | [diff] [blame] | 134 | printf ("Board: KUP4K Rev %d.%d\n",rev,mod); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 135 | return (0); |
| 136 | } |
| 137 | |
| 138 | /* ------------------------------------------------------------------------- */ |
| 139 | |
| 140 | long int initdram (int board_type) |
| 141 | { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 142 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
| 143 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
| 144 | long int size_b0 = 0; |
| 145 | long int size_b1 = 0; |
| 146 | long int size_b2 = 0; |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 147 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 148 | upmconfig (UPMA, (uint *) sdram_table, |
| 149 | sizeof (sdram_table) / sizeof (uint)); |
| 150 | |
| 151 | /* |
| 152 | * Preliminary prescaler for refresh (depends on number of |
| 153 | * banks): This value is selected for four cycles every 62.4 us |
| 154 | * with two SDRAM banks or four cycles every 31.2 us with one |
| 155 | * bank. It will be adjusted after memory sizing. |
| 156 | */ |
| 157 | memctl->memc_mptpr = CFG_MPTPR; |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 158 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 159 | memctl->memc_mar = 0x00000088; |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 160 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 161 | /* |
| 162 | * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at |
| 163 | * preliminary addresses - these have to be modified after the |
| 164 | * SDRAM size has been determined. |
| 165 | */ |
| 166 | /* memctl->memc_or1 = CFG_OR1_PRELIM; */ |
| 167 | /* memctl->memc_br1 = CFG_BR1_PRELIM; */ |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 168 | |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 169 | /* memctl->memc_or2 = CFG_OR2_PRELIM; */ |
| 170 | /* memctl->memc_br2 = CFG_BR2_PRELIM; */ |
| 171 | |
| 172 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 173 | memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 174 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 175 | udelay (200); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 176 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 177 | /* perform SDRAM initializsation sequence */ |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 178 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 179 | memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
| 180 | udelay (1); |
| 181 | memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */ |
| 182 | udelay (1); |
| 183 | memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */ |
| 184 | udelay (1); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 185 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 186 | memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ |
| 187 | udelay (1); |
| 188 | memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */ |
| 189 | udelay (1); |
| 190 | memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */ |
| 191 | udelay (1); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 192 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 193 | memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ |
| 194 | udelay (1); |
| 195 | memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */ |
| 196 | udelay (1); |
| 197 | memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ |
| 198 | udelay (1); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 199 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 200 | memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ |
| 201 | udelay (1000); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 202 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 203 | #if 0 /* 3 x 8MB */ |
| 204 | size_b0 = 0x00800000; |
| 205 | size_b1 = 0x00800000; |
| 206 | size_b2 = 0x00800000; |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 207 | memctl->memc_mptpr = CFG_MPTPR; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 208 | udelay (1000); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 209 | memctl->memc_or1 = 0xFF800A00; |
| 210 | memctl->memc_br1 = 0x00000081; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 211 | memctl->memc_or2 = 0xFF000A00; |
| 212 | memctl->memc_br2 = 0x00800081; |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 213 | memctl->memc_or3 = 0xFE000A00; |
| 214 | memctl->memc_br3 = 0x01000081; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 215 | #else /* 3 x 16 MB */ |
| 216 | size_b0 = 0x01000000; |
| 217 | size_b1 = 0x01000000; |
| 218 | size_b2 = 0x01000000; |
| 219 | memctl->memc_mptpr = CFG_MPTPR; |
| 220 | udelay (1000); |
| 221 | memctl->memc_or1 = 0xFF000A00; |
| 222 | memctl->memc_br1 = 0x00000081; |
| 223 | memctl->memc_or2 = 0xFE000A00; |
| 224 | memctl->memc_br2 = 0x01000081; |
| 225 | memctl->memc_or3 = 0xFC000A00; |
| 226 | memctl->memc_br3 = 0x02000081; |
| 227 | #endif |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 228 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 229 | udelay (10000); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 230 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 231 | return (size_b0 + size_b1 + size_b2); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | /* ------------------------------------------------------------------------- */ |
| 235 | |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 236 | int misc_init_r (void) |
| 237 | { |
wdenk | 90e7e42 | 2002-12-04 23:39:58 +0000 | [diff] [blame] | 238 | #ifdef CONFIG_STATUS_LED |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 239 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
wdenk | 90e7e42 | 2002-12-04 23:39:58 +0000 | [diff] [blame] | 240 | #endif |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 241 | #ifdef CONFIG_KUP4K_LOGO |
| 242 | bd_t *bd = gd->bd; |
| 243 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 244 | lcd_logo (bd); |
| 245 | #endif /* CONFIG_KUP4K_LOGO */ |
wdenk | 90e7e42 | 2002-12-04 23:39:58 +0000 | [diff] [blame] | 246 | #ifdef CONFIG_IDE_LED |
| 247 | /* Configure PA8 as output port */ |
| 248 | immap->im_ioport.iop_padir |= 0x80; |
| 249 | immap->im_ioport.iop_paodr |= 0x80; |
| 250 | immap->im_ioport.iop_papar &= ~0x80; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 251 | immap->im_ioport.iop_padat |= 0x80; /* turn it off */ |
wdenk | 90e7e42 | 2002-12-04 23:39:58 +0000 | [diff] [blame] | 252 | #endif |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 253 | setenv("hw","4k"); |
| 254 | poweron_key(); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 255 | return (0); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 256 | } |
| 257 | |
| 258 | #ifdef CONFIG_KUP4K_LOGO |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 259 | |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 260 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 261 | void lcd_logo (bd_t * bd) |
| 262 | { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 263 | FB_INFO_S1D13xxx fb_info; |
| 264 | S1D_INDEX s1dReg; |
| 265 | S1D_VALUE s1dValue; |
| 266 | volatile immap_t *immr = (immap_t *) CFG_IMMR; |
| 267 | volatile memctl8xx_t *memctl; |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 268 | ushort i; |
| 269 | uchar *fb; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 270 | int rs, gs, bs; |
| 271 | int r = 8, g = 8, b = 4; |
| 272 | int r1, g1, b1; |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 273 | int n; |
Wolfgang Denk | 7fb5266 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 274 | char tmp[64]; /* long enough for environment variables */ |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 275 | int tft = 0; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 276 | |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 277 | immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM); |
| 278 | immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM); |
| 279 | immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */ |
| 280 | immr->im_cpm.cp_pbdir |= (PB_LCD_PWM); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 281 | |
| 282 | /*----------------------------------------------------------------------------- */ |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 283 | /* Initialize the chip and the frame buffer driver. */ |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 284 | /*----------------------------------------------------------------------------- */ |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 285 | memctl = &immr->im_memctl; |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 286 | |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 287 | |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 288 | /* |
| 289 | * Init ChipSelect #5 (S1D13768) |
| 290 | */ |
| 291 | memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */ |
| 292 | memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */ |
wdenk | e07ec1b | 2004-05-12 22:54:36 +0000 | [diff] [blame] | 293 | __asm__ ("eieio"); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 294 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 295 | fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR); |
| 296 | fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 297 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 298 | if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28) |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 299 | || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 300 | printf ("Warning:LCD Controller S1D13706 not found\n"); |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 301 | setenv ("lcd", "none"); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 302 | return; |
| 303 | } |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 304 | |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 305 | |
| 306 | for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) { |
| 307 | s1dReg = aS1DRegs_prelimn[i].Index; |
| 308 | s1dValue = aS1DRegs_prelimn[i].Value; |
| 309 | debugk ("s13768 reg: %02x value: %02x\n", |
| 310 | aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 311 | ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 312 | s1dValue; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 313 | } |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 314 | |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 315 | |
| 316 | n = getenv_r ("lcd", tmp, sizeof (tmp)); |
| 317 | if (n > 0) { |
| 318 | if (!strcmp ("tft", tmp)) |
| 319 | tft = 1; |
| 320 | else |
| 321 | tft = 0; |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 322 | } |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 323 | #if 0 |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 324 | if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04) |
| 325 | tft = 0; |
| 326 | else |
| 327 | tft = 1; |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 328 | #endif |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 329 | |
| 330 | debugk ("Port=0x%02x -> TFT=%d\n", tft, |
| 331 | ((S1D_VALUE *) fb_info.RegAddr)[0xAC]); |
| 332 | |
| 333 | /* init controller */ |
| 334 | if (!tft) { |
| 335 | for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) { |
| 336 | s1dReg = aS1DRegs_stn[i].Index; |
| 337 | s1dValue = aS1DRegs_stn[i].Value; |
| 338 | debugk ("s13768 reg: %02x value: %02x\n", |
| 339 | aS1DRegs_stn[i].Index, |
| 340 | aS1DRegs_stn[i].Value); |
| 341 | ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] = |
| 342 | s1dValue; |
| 343 | } |
| 344 | n = getenv_r ("contrast", tmp, sizeof (tmp)); |
| 345 | ((S1D_VALUE *) fb_info.RegAddr)[0xB3] = |
| 346 | (n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0; |
| 347 | switch (bd->bi_busfreq) { |
| 348 | case 40000000: |
| 349 | ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; |
| 350 | ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41; |
| 351 | break; |
| 352 | case 48000000: |
| 353 | ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; |
| 354 | ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; |
| 355 | break; |
| 356 | default: |
| 357 | printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); |
| 358 | case 64000000: |
| 359 | ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; |
| 360 | ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66; |
| 361 | break; |
| 362 | } |
| 363 | /* setenv("lcd","stn"); */ |
| 364 | } else { |
| 365 | for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) { |
| 366 | s1dReg = aS1DRegs_tft[i].Index; |
| 367 | s1dValue = aS1DRegs_tft[i].Value; |
| 368 | debugk ("s13768 reg: %02x value: %02x\n", |
| 369 | aS1DRegs_tft[i].Index, |
| 370 | aS1DRegs_tft[i].Value); |
| 371 | ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = |
| 372 | s1dValue; |
| 373 | } |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 374 | |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 375 | switch (bd->bi_busfreq) { |
| 376 | default: |
| 377 | printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); |
| 378 | case 40000000: |
| 379 | ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42; |
| 380 | ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30; |
| 381 | break; |
| 382 | } |
| 383 | /* setenv("lcd","tft"); */ |
| 384 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 385 | |
| 386 | /* create and set colormap */ |
| 387 | rs = 256 / (r - 1); |
| 388 | gs = 256 / (g - 1); |
| 389 | bs = 256 / (b - 1); |
| 390 | for (i = 0; i < 256; i++) { |
| 391 | r1 = (rs * ((i / (g * b)) % r)) * 255; |
| 392 | g1 = (gs * ((i / b) % g)) * 255; |
| 393 | b1 = (bs * ((i) % b)) * 255; |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 394 | debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 395 | S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4), |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 396 | (b1 >> 4)); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 397 | } |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 398 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 399 | /* copy bitmap */ |
Wolfgang Denk | 7fb5266 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 400 | fb = (uchar *) (fb_info.VmemAddr); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 401 | memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240); |
wdenk | 56f94be | 2002-11-05 16:35:14 +0000 | [diff] [blame] | 402 | } |
wdenk | 65faef9 | 2004-03-25 19:29:38 +0000 | [diff] [blame] | 403 | #endif /* CONFIG_KUP4K_LOGO */ |