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wdenk56f94be2002-11-05 16:35:14 +00001/*
wdenk65faef92004-03-25 19:29:38 +00002 * (C) Copyright 2000-2004
wdenk56f94be2002-11-05 16:35:14 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <mpc8xx.h>
wdenk65faef92004-03-25 19:29:38 +000027#include "../common/kup.h"
wdenk56f94be2002-11-05 16:35:14 +000028#ifdef CONFIG_KUP4K_LOGO
29 #include "s1d13706.h"
30#endif
31
Wolfgang Denk6405a152006-03-31 18:32:53 +020032DECLARE_GLOBAL_DATA_PTR;
33
wdenk65faef92004-03-25 19:29:38 +000034#undef DEBUG
35#ifdef DEBUG
36# define debugk(fmt,args...) printf(fmt ,##args)
37#else
38# define debugk(fmt,args...)
39#endif
wdenk56f94be2002-11-05 16:35:14 +000040
wdenk65faef92004-03-25 19:29:38 +000041typedef struct {
42 volatile unsigned char *VmemAddr;
43 volatile unsigned char *RegAddr;
44} FB_INFO_S1D13xxx;
45
wdenk56f94be2002-11-05 16:35:14 +000046
47/* ------------------------------------------------------------------------- */
48
wdenk56f94be2002-11-05 16:35:14 +000049#ifdef CONFIG_KUP4K_LOGO
wdenk65faef92004-03-25 19:29:38 +000050void lcd_logo(bd_t *bd);
wdenk56f94be2002-11-05 16:35:14 +000051#endif
52
wdenk65faef92004-03-25 19:29:38 +000053
wdenk56f94be2002-11-05 16:35:14 +000054/* ------------------------------------------------------------------------- */
55
56#define _NOT_USED_ 0xFFFFFFFF
57
wdenk65faef92004-03-25 19:29:38 +000058const uint sdram_table[] = {
wdenk56f94be2002-11-05 16:35:14 +000059 /*
60 * Single Read. (Offset 0 in UPMA RAM)
61 */
wdenk4e112c12003-06-03 23:54:09 +000062 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
wdenk56f94be2002-11-05 16:35:14 +000063 0x1FF77C47, /* last */
64
65 /*
66 * SDRAM Initialization (offset 5 in UPMA RAM)
67 *
68 * This is no UPM entry point. The following definition uses
69 * the remaining space to establish an initialization
70 * sequence, which is executed by a RUN command.
71 *
72 */
wdenk4e112c12003-06-03 23:54:09 +000073 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
wdenk56f94be2002-11-05 16:35:14 +000074
75 /*
76 * Burst Read. (Offset 8 in UPMA RAM)
77 */
wdenk4e112c12003-06-03 23:54:09 +000078 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
79 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
wdenk56f94be2002-11-05 16:35:14 +000080 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82
83 /*
84 * Single Write. (Offset 18 in UPMA RAM)
85 */
wdenk4e112c12003-06-03 23:54:09 +000086 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
wdenk56f94be2002-11-05 16:35:14 +000087 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
88
89 /*
90 * Burst Write. (Offset 20 in UPMA RAM)
91 */
wdenk4e112c12003-06-03 23:54:09 +000092 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
93 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
94 _NOT_USED_,
wdenk56f94be2002-11-05 16:35:14 +000095 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
96 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
97
98 /*
99 * Refresh (Offset 30 in UPMA RAM)
100 */
wdenk4e112c12003-06-03 23:54:09 +0000101 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
102 0xFFFFFC84, 0xFFFFFC07, /* last */
103 _NOT_USED_, _NOT_USED_,
wdenk56f94be2002-11-05 16:35:14 +0000104 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
105
106 /*
107 * Exception. (Offset 3c in UPMA RAM)
108 */
109 0x7FFFFC07, /* last */
110 _NOT_USED_, _NOT_USED_, _NOT_USED_,
111};
112
113/* ------------------------------------------------------------------------- */
114
115
116/*
117 * Check Board Identity:
118 */
119
120int checkboard (void)
121{
wdenk65faef92004-03-25 19:29:38 +0000122 volatile immap_t *immap = (immap_t *) CFG_IMMR;
123 uchar *latch,rev,mod;
wdenk56f94be2002-11-05 16:35:14 +0000124
wdenk65faef92004-03-25 19:29:38 +0000125 /*
126 * Init ChipSelect #4 (CAN + HW-Latch)
127 */
128 immap->im_memctl.memc_or4 = 0xFFFF8926;
129 immap->im_memctl.memc_br4 = 0x90000401;
wdenke07ec1b2004-05-12 22:54:36 +0000130 __asm__ ("eieio");
wdenk65faef92004-03-25 19:29:38 +0000131 latch=(uchar *)0x90000200;
132 rev = (*latch & 0xF8) >> 3;
133 mod=(*latch & 0x03);
wdenke07ec1b2004-05-12 22:54:36 +0000134 printf ("Board: KUP4K Rev %d.%d\n",rev,mod);
wdenk56f94be2002-11-05 16:35:14 +0000135 return (0);
136}
137
138/* ------------------------------------------------------------------------- */
139
140long int initdram (int board_type)
141{
wdenk4e112c12003-06-03 23:54:09 +0000142 volatile immap_t *immap = (immap_t *) CFG_IMMR;
143 volatile memctl8xx_t *memctl = &immap->im_memctl;
144 long int size_b0 = 0;
145 long int size_b1 = 0;
146 long int size_b2 = 0;
wdenk56f94be2002-11-05 16:35:14 +0000147
wdenk4e112c12003-06-03 23:54:09 +0000148 upmconfig (UPMA, (uint *) sdram_table,
149 sizeof (sdram_table) / sizeof (uint));
150
151 /*
152 * Preliminary prescaler for refresh (depends on number of
153 * banks): This value is selected for four cycles every 62.4 us
154 * with two SDRAM banks or four cycles every 31.2 us with one
155 * bank. It will be adjusted after memory sizing.
156 */
157 memctl->memc_mptpr = CFG_MPTPR;
wdenk56f94be2002-11-05 16:35:14 +0000158
wdenk4e112c12003-06-03 23:54:09 +0000159 memctl->memc_mar = 0x00000088;
wdenk56f94be2002-11-05 16:35:14 +0000160
wdenk4e112c12003-06-03 23:54:09 +0000161 /*
162 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
163 * preliminary addresses - these have to be modified after the
164 * SDRAM size has been determined.
165 */
166/* memctl->memc_or1 = CFG_OR1_PRELIM; */
167/* memctl->memc_br1 = CFG_BR1_PRELIM; */
wdenk56f94be2002-11-05 16:35:14 +0000168
wdenk56f94be2002-11-05 16:35:14 +0000169/* memctl->memc_or2 = CFG_OR2_PRELIM; */
170/* memctl->memc_br2 = CFG_BR2_PRELIM; */
171
172
wdenk4e112c12003-06-03 23:54:09 +0000173 memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
wdenk56f94be2002-11-05 16:35:14 +0000174
wdenk4e112c12003-06-03 23:54:09 +0000175 udelay (200);
wdenk56f94be2002-11-05 16:35:14 +0000176
wdenk4e112c12003-06-03 23:54:09 +0000177 /* perform SDRAM initializsation sequence */
wdenk56f94be2002-11-05 16:35:14 +0000178
wdenk4e112c12003-06-03 23:54:09 +0000179 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
180 udelay (1);
181 memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
182 udelay (1);
183 memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
184 udelay (1);
wdenk56f94be2002-11-05 16:35:14 +0000185
wdenk4e112c12003-06-03 23:54:09 +0000186 memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
187 udelay (1);
188 memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
189 udelay (1);
190 memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
191 udelay (1);
wdenk56f94be2002-11-05 16:35:14 +0000192
wdenk4e112c12003-06-03 23:54:09 +0000193 memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
194 udelay (1);
195 memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
196 udelay (1);
197 memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
198 udelay (1);
wdenk56f94be2002-11-05 16:35:14 +0000199
wdenk4e112c12003-06-03 23:54:09 +0000200 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
201 udelay (1000);
wdenk56f94be2002-11-05 16:35:14 +0000202
wdenk4e112c12003-06-03 23:54:09 +0000203#if 0 /* 3 x 8MB */
204 size_b0 = 0x00800000;
205 size_b1 = 0x00800000;
206 size_b2 = 0x00800000;
wdenk56f94be2002-11-05 16:35:14 +0000207 memctl->memc_mptpr = CFG_MPTPR;
wdenk4e112c12003-06-03 23:54:09 +0000208 udelay (1000);
wdenk56f94be2002-11-05 16:35:14 +0000209 memctl->memc_or1 = 0xFF800A00;
210 memctl->memc_br1 = 0x00000081;
wdenk4e112c12003-06-03 23:54:09 +0000211 memctl->memc_or2 = 0xFF000A00;
212 memctl->memc_br2 = 0x00800081;
wdenk56f94be2002-11-05 16:35:14 +0000213 memctl->memc_or3 = 0xFE000A00;
214 memctl->memc_br3 = 0x01000081;
wdenk4e112c12003-06-03 23:54:09 +0000215#else /* 3 x 16 MB */
216 size_b0 = 0x01000000;
217 size_b1 = 0x01000000;
218 size_b2 = 0x01000000;
219 memctl->memc_mptpr = CFG_MPTPR;
220 udelay (1000);
221 memctl->memc_or1 = 0xFF000A00;
222 memctl->memc_br1 = 0x00000081;
223 memctl->memc_or2 = 0xFE000A00;
224 memctl->memc_br2 = 0x01000081;
225 memctl->memc_or3 = 0xFC000A00;
226 memctl->memc_br3 = 0x02000081;
227#endif
wdenk56f94be2002-11-05 16:35:14 +0000228
wdenk4e112c12003-06-03 23:54:09 +0000229 udelay (10000);
wdenk56f94be2002-11-05 16:35:14 +0000230
wdenk4e112c12003-06-03 23:54:09 +0000231 return (size_b0 + size_b1 + size_b2);
wdenk56f94be2002-11-05 16:35:14 +0000232}
233
234/* ------------------------------------------------------------------------- */
235
wdenk56f94be2002-11-05 16:35:14 +0000236int misc_init_r (void)
237{
wdenk90e7e422002-12-04 23:39:58 +0000238#ifdef CONFIG_STATUS_LED
wdenk4e112c12003-06-03 23:54:09 +0000239 volatile immap_t *immap = (immap_t *) CFG_IMMR;
wdenk90e7e422002-12-04 23:39:58 +0000240#endif
wdenk56f94be2002-11-05 16:35:14 +0000241#ifdef CONFIG_KUP4K_LOGO
242 bd_t *bd = gd->bd;
243
wdenk4e112c12003-06-03 23:54:09 +0000244 lcd_logo (bd);
245#endif /* CONFIG_KUP4K_LOGO */
wdenk90e7e422002-12-04 23:39:58 +0000246#ifdef CONFIG_IDE_LED
247 /* Configure PA8 as output port */
248 immap->im_ioport.iop_padir |= 0x80;
249 immap->im_ioport.iop_paodr |= 0x80;
250 immap->im_ioport.iop_papar &= ~0x80;
wdenk4e112c12003-06-03 23:54:09 +0000251 immap->im_ioport.iop_padat |= 0x80; /* turn it off */
wdenk90e7e422002-12-04 23:39:58 +0000252#endif
wdenk65faef92004-03-25 19:29:38 +0000253 setenv("hw","4k");
254 poweron_key();
wdenk4e112c12003-06-03 23:54:09 +0000255 return (0);
wdenk56f94be2002-11-05 16:35:14 +0000256}
257
258#ifdef CONFIG_KUP4K_LOGO
wdenk4e112c12003-06-03 23:54:09 +0000259
wdenk56f94be2002-11-05 16:35:14 +0000260
wdenk4e112c12003-06-03 23:54:09 +0000261void lcd_logo (bd_t * bd)
262{
wdenk4e112c12003-06-03 23:54:09 +0000263 FB_INFO_S1D13xxx fb_info;
264 S1D_INDEX s1dReg;
265 S1D_VALUE s1dValue;
266 volatile immap_t *immr = (immap_t *) CFG_IMMR;
267 volatile memctl8xx_t *memctl;
wdenk56f94be2002-11-05 16:35:14 +0000268 ushort i;
269 uchar *fb;
wdenk4e112c12003-06-03 23:54:09 +0000270 int rs, gs, bs;
271 int r = 8, g = 8, b = 4;
272 int r1, g1, b1;
wdenk65faef92004-03-25 19:29:38 +0000273 int n;
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200274 char tmp[64]; /* long enough for environment variables */
wdenk65faef92004-03-25 19:29:38 +0000275 int tft = 0;
wdenk4e112c12003-06-03 23:54:09 +0000276
wdenk65faef92004-03-25 19:29:38 +0000277 immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM);
278 immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM);
279 immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */
280 immr->im_cpm.cp_pbdir |= (PB_LCD_PWM);
wdenk56f94be2002-11-05 16:35:14 +0000281
282/*----------------------------------------------------------------------------- */
wdenk56f94be2002-11-05 16:35:14 +0000283/* Initialize the chip and the frame buffer driver. */
wdenk56f94be2002-11-05 16:35:14 +0000284/*----------------------------------------------------------------------------- */
wdenk65faef92004-03-25 19:29:38 +0000285 memctl = &immr->im_memctl;
wdenk56f94be2002-11-05 16:35:14 +0000286
wdenk56f94be2002-11-05 16:35:14 +0000287
wdenk65faef92004-03-25 19:29:38 +0000288 /*
289 * Init ChipSelect #5 (S1D13768)
290 */
291 memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */
292 memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
wdenke07ec1b2004-05-12 22:54:36 +0000293 __asm__ ("eieio");
wdenk56f94be2002-11-05 16:35:14 +0000294
wdenk4e112c12003-06-03 23:54:09 +0000295 fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
296 fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
wdenk56f94be2002-11-05 16:35:14 +0000297
wdenk4e112c12003-06-03 23:54:09 +0000298 if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
wdenk65faef92004-03-25 19:29:38 +0000299 || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
wdenk4e112c12003-06-03 23:54:09 +0000300 printf ("Warning:LCD Controller S1D13706 not found\n");
wdenk65faef92004-03-25 19:29:38 +0000301 setenv ("lcd", "none");
wdenk4e112c12003-06-03 23:54:09 +0000302 return;
303 }
wdenk56f94be2002-11-05 16:35:14 +0000304
wdenk65faef92004-03-25 19:29:38 +0000305
306 for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) {
307 s1dReg = aS1DRegs_prelimn[i].Index;
308 s1dValue = aS1DRegs_prelimn[i].Value;
309 debugk ("s13768 reg: %02x value: %02x\n",
310 aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value);
wdenk4e112c12003-06-03 23:54:09 +0000311 ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
wdenk65faef92004-03-25 19:29:38 +0000312 s1dValue;
wdenk4e112c12003-06-03 23:54:09 +0000313 }
wdenk56f94be2002-11-05 16:35:14 +0000314
wdenk65faef92004-03-25 19:29:38 +0000315
316 n = getenv_r ("lcd", tmp, sizeof (tmp));
317 if (n > 0) {
318 if (!strcmp ("tft", tmp))
319 tft = 1;
320 else
321 tft = 0;
wdenk56f94be2002-11-05 16:35:14 +0000322 }
wdenk56f94be2002-11-05 16:35:14 +0000323#if 0
wdenk65faef92004-03-25 19:29:38 +0000324 if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04)
325 tft = 0;
326 else
327 tft = 1;
wdenk56f94be2002-11-05 16:35:14 +0000328#endif
wdenk65faef92004-03-25 19:29:38 +0000329
330 debugk ("Port=0x%02x -> TFT=%d\n", tft,
331 ((S1D_VALUE *) fb_info.RegAddr)[0xAC]);
332
333 /* init controller */
334 if (!tft) {
335 for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) {
336 s1dReg = aS1DRegs_stn[i].Index;
337 s1dValue = aS1DRegs_stn[i].Value;
338 debugk ("s13768 reg: %02x value: %02x\n",
339 aS1DRegs_stn[i].Index,
340 aS1DRegs_stn[i].Value);
341 ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] =
342 s1dValue;
343 }
344 n = getenv_r ("contrast", tmp, sizeof (tmp));
345 ((S1D_VALUE *) fb_info.RegAddr)[0xB3] =
346 (n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0;
347 switch (bd->bi_busfreq) {
348 case 40000000:
349 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
350 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
351 break;
352 case 48000000:
353 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
354 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
355 break;
356 default:
357 printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
358 case 64000000:
359 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
360 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
361 break;
362 }
363 /* setenv("lcd","stn"); */
364 } else {
365 for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) {
366 s1dReg = aS1DRegs_tft[i].Index;
367 s1dValue = aS1DRegs_tft[i].Value;
368 debugk ("s13768 reg: %02x value: %02x\n",
369 aS1DRegs_tft[i].Index,
370 aS1DRegs_tft[i].Value);
371 ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
372 s1dValue;
373 }
wdenk56f94be2002-11-05 16:35:14 +0000374
wdenk65faef92004-03-25 19:29:38 +0000375 switch (bd->bi_busfreq) {
376 default:
377 printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
378 case 40000000:
379 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42;
380 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30;
381 break;
382 }
383 /* setenv("lcd","tft"); */
384 }
wdenk4e112c12003-06-03 23:54:09 +0000385
386 /* create and set colormap */
387 rs = 256 / (r - 1);
388 gs = 256 / (g - 1);
389 bs = 256 / (b - 1);
390 for (i = 0; i < 256; i++) {
391 r1 = (rs * ((i / (g * b)) % r)) * 255;
392 g1 = (gs * ((i / b) % g)) * 255;
393 b1 = (bs * ((i) % b)) * 255;
wdenk65faef92004-03-25 19:29:38 +0000394 debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4);
wdenk4e112c12003-06-03 23:54:09 +0000395 S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
wdenk65faef92004-03-25 19:29:38 +0000396 (b1 >> 4));
wdenk4e112c12003-06-03 23:54:09 +0000397 }
wdenk56f94be2002-11-05 16:35:14 +0000398
wdenk4e112c12003-06-03 23:54:09 +0000399 /* copy bitmap */
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200400 fb = (uchar *) (fb_info.VmemAddr);
wdenk4e112c12003-06-03 23:54:09 +0000401 memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
wdenk56f94be2002-11-05 16:35:14 +0000402}
wdenk65faef92004-03-25 19:29:38 +0000403#endif /* CONFIG_KUP4K_LOGO */