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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChung Liewf6afe722007-06-18 13:50:13 -05002/*
3 *
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
Alison Wang35d23df2012-03-26 21:49:05 +00007 * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
TsiChung Liewf6afe722007-06-18 13:50:13 -05008 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewf6afe722007-06-18 13:50:13 -05009 */
10
11#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -070012#include <clock_legacy.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
TsiChung Liewf6afe722007-06-18 13:50:13 -050014#include <asm/processor.h>
15
TsiChungLiew2ce14b72007-07-05 23:05:31 -050016#include <asm/immap.h>
Alison Wang35d23df2012-03-26 21:49:05 +000017#include <asm/io.h>
TsiChung Liewf6afe722007-06-18 13:50:13 -050018
Wolfgang Denkd112a2c2007-09-15 20:48:41 +020019DECLARE_GLOBAL_DATA_PTR;
20
TsiChung Liewf6afe722007-06-18 13:50:13 -050021/* PLL min/max specifications */
TsiChungLiew2ce14b72007-07-05 23:05:31 -050022#define MAX_FVCO 500000 /* KHz */
23#define MAX_FSYS 80000 /* KHz */
24#define MIN_FSYS 58333 /* KHz */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000025
26#ifdef CONFIG_MCF5301x
27#define FREF 20000 /* KHz */
28#define MAX_MFD 63 /* Multiplier */
29#define MIN_MFD 0 /* Multiplier */
30#define USBDIV 8
31
32/* Low Power Divider specifications */
33#define MIN_LPD (0) /* Divider (not encoded) */
34#define MAX_LPD (15) /* Divider (not encoded) */
35#define DEFAULT_LPD (0) /* Divider (not encoded) */
36#endif
37
38#ifdef CONFIG_MCF532x
TsiChungLiew2ce14b72007-07-05 23:05:31 -050039#define FREF 16000 /* KHz */
40#define MAX_MFD 135 /* Multiplier */
41#define MIN_MFD 88 /* Multiplier */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000042
43/* Low Power Divider specifications */
TsiChungLiew2ce14b72007-07-05 23:05:31 -050044#define MIN_LPD (1 << 0) /* Divider (not encoded) */
45#define MAX_LPD (1 << 15) /* Divider (not encoded) */
46#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000047#endif
TsiChung Liewf6afe722007-06-18 13:50:13 -050048
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000049#define BUSDIV 6 /* Divider */
50
51/* Get the value of the current system clock */
TsiChung Liewf6afe722007-06-18 13:50:13 -050052int get_sys_clock(void)
53{
Alison Wang35d23df2012-03-26 21:49:05 +000054 ccm_t *ccm = (ccm_t *)(MMAP_CCM);
55 pll_t *pll = (pll_t *)(MMAP_PLL);
TsiChung Liewf6afe722007-06-18 13:50:13 -050056 int divider;
57
58 /* Test to see if device is in LIMP mode */
Alison Wang35d23df2012-03-26 21:49:05 +000059 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) {
60 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000061#ifdef CONFIG_MCF5301x
62 return (FREF / (3 * (1 << divider)));
63#endif
64#ifdef CONFIG_MCF532x
TsiChung Liewf6afe722007-06-18 13:50:13 -050065 return (FREF / (2 << divider));
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000066#endif
TsiChung Liewf6afe722007-06-18 13:50:13 -050067 } else {
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000068#ifdef CONFIG_MCF5301x
Alison Wang35d23df2012-03-26 21:49:05 +000069 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1;
70 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8));
71 u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1;
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000072
73 return (((FREF * pfdr) / refdiv) / busdiv);
74#endif
75#ifdef CONFIG_MCF532x
Alison Wang35d23df2012-03-26 21:49:05 +000076 return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000077#endif
TsiChung Liewf6afe722007-06-18 13:50:13 -050078 }
79}
80
81/*
82 * Initialize the Low Power Divider circuit
83 *
84 * Parameters:
85 * div Desired system frequency divider
86 *
87 * Return Value:
88 * The resulting output system frequency
89 */
90int clock_limp(int div)
91{
Alison Wang35d23df2012-03-26 21:49:05 +000092 ccm_t *ccm = (ccm_t *)(MMAP_CCM);
TsiChung Liewf6afe722007-06-18 13:50:13 -050093 u32 temp;
94
95 /* Check bounds of divider */
96 if (div < MIN_LPD)
97 div = MIN_LPD;
98 if (div > MAX_LPD)
99 div = MAX_LPD;
100
101 /* Save of the current value of the SSIDIV so we don't overwrite the value */
Alison Wang35d23df2012-03-26 21:49:05 +0000102 temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF));
TsiChung Liewf6afe722007-06-18 13:50:13 -0500103
104 /* Apply the divider to the system clock */
Alison Wang35d23df2012-03-26 21:49:05 +0000105 out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
TsiChung Liewf6afe722007-06-18 13:50:13 -0500106
Alison Wang35d23df2012-03-26 21:49:05 +0000107 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
TsiChung Liewf6afe722007-06-18 13:50:13 -0500108
109 return (FREF / (3 * (1 << div)));
110}
111
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000112/* Exit low power LIMP mode */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500113int clock_exit_limp(void)
114{
Alison Wang35d23df2012-03-26 21:49:05 +0000115 ccm_t *ccm = (ccm_t *)(MMAP_CCM);
TsiChung Liewf6afe722007-06-18 13:50:13 -0500116 int fout;
117
118 /* Exit LIMP mode */
Alison Wang35d23df2012-03-26 21:49:05 +0000119 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
TsiChung Liewf6afe722007-06-18 13:50:13 -0500120
121 /* Wait for PLL to lock */
Alison Wang35d23df2012-03-26 21:49:05 +0000122 while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK))
123 ;
TsiChung Liewf6afe722007-06-18 13:50:13 -0500124
125 fout = get_sys_clock();
126
127 return fout;
128}
129
130/* Initialize the PLL
131 *
132 * Parameters:
133 * fref PLL reference clock frequency in KHz
134 * fsys Desired PLL output frequency in KHz
135 * flags Operating parameters
136 *
137 * Return Value:
138 * The resulting output system frequency
139 */
140int clock_pll(int fsys, int flags)
141{
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000142#ifdef CONFIG_MCF532x
Alison Wang35d23df2012-03-26 21:49:05 +0000143 u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000144#endif
Alison Wang35d23df2012-03-26 21:49:05 +0000145 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
146 pll_t *pll = (pll_t *)(MMAP_PLL);
TsiChung Liewf6afe722007-06-18 13:50:13 -0500147 int fref, temp, fout, mfd;
148 u32 i;
149
150 fref = FREF;
151
152 if (fsys == 0) {
153 /* Return current PLL output */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000154#ifdef CONFIG_MCF5301x
Alison Wang35d23df2012-03-26 21:49:05 +0000155 u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1;
156 mfd = (in_be32(&pll->pcr) & 0x3F) + 1;
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000157
158 return (fref * mfd) / busdiv;
159#endif
160#ifdef CONFIG_MCF532x
Alison Wang35d23df2012-03-26 21:49:05 +0000161 mfd = in_8(&pll->pfdr);
TsiChung Liewf6afe722007-06-18 13:50:13 -0500162
163 return (fref * mfd / (BUSDIV * 4));
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000164#endif
TsiChung Liewf6afe722007-06-18 13:50:13 -0500165 }
166
167 /* Check bounds of requested system clock */
168 if (fsys > MAX_FSYS)
169 fsys = MAX_FSYS;
170
171 if (fsys < MIN_FSYS)
172 fsys = MIN_FSYS;
173
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000174 /*
175 * Multiplying by 100 when calculating the temp value,
176 * and then dividing by 100 to calculate the mfd allows
177 * for exact values without needing to include floating
178 * point libraries.
179 */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500180 temp = (100 * fsys) / fref;
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000181#ifdef CONFIG_MCF5301x
182 mfd = (BUSDIV * temp) / 100;
183
184 /* Determine the output frequency for selected values */
185 fout = ((fref * mfd) / BUSDIV);
186#endif
187#ifdef CONFIG_MCF532x
TsiChung Liewf6afe722007-06-18 13:50:13 -0500188 mfd = (4 * BUSDIV * temp) / 100;
189
190 /* Determine the output frequency for selected values */
191 fout = ((fref * mfd) / (BUSDIV * 4));
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000192#endif
TsiChung Liewf6afe722007-06-18 13:50:13 -0500193
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +0100194/* must not tamper with SDRAMC if running from SDRAM */
195#if !defined(CONFIG_MONITOR_IS_IN_RAM)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500196 /*
197 * Check to see if the SDRAM has already been initialized.
198 * If it has then the SDRAM needs to be put into self refresh
199 * mode before reprogramming the PLL.
200 */
Alison Wang35d23df2012-03-26 21:49:05 +0000201 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
202 clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
TsiChung Liewf6afe722007-06-18 13:50:13 -0500203
204 /*
205 * Initialize the PLL to generate the new system clock frequency.
206 * The device must be put into LIMP mode to reprogram the PLL.
207 */
208
209 /* Enter LIMP mode */
210 clock_limp(DEFAULT_LPD);
211
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000212#ifdef CONFIG_MCF5301x
Alison Wang35d23df2012-03-26 21:49:05 +0000213 out_be32(&pll->pdr,
214 PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
215 PLL_PDR_OUTDIV2(BUSDIV - 1) |
216 PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
217 PLL_PDR_OUTDIV4(USBDIV - 1));
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000218
Alison Wang35d23df2012-03-26 21:49:05 +0000219 clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK);
220 setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1));
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000221#endif
222#ifdef CONFIG_MCF532x
TsiChung Liewf6afe722007-06-18 13:50:13 -0500223 /* Reprogram PLL for desired fsys */
Alison Wang35d23df2012-03-26 21:49:05 +0000224 out_8(&pll->podr,
225 PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
TsiChung Liewf6afe722007-06-18 13:50:13 -0500226
Alison Wang35d23df2012-03-26 21:49:05 +0000227 out_8(&pll->pfdr, mfd);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000228#endif
TsiChung Liewf6afe722007-06-18 13:50:13 -0500229
230 /* Exit LIMP mode */
231 clock_exit_limp();
232
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000233 /* Return the SDRAM to normal operation if it is in use. */
Alison Wang35d23df2012-03-26 21:49:05 +0000234 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
235 setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000236
237#ifdef CONFIG_MCF532x
TsiChung Liewf6afe722007-06-18 13:50:13 -0500238 /*
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000239 * software workaround for SDRAM opeartion after exiting LIMP
240 * mode errata
TsiChung Liewf6afe722007-06-18 13:50:13 -0500241 */
Tom Rinibb4dd962022-11-16 13:10:37 -0500242 out_be32(sdram_workaround, CFG_SYS_SDRAM_BASE);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000243#endif
TsiChungLiew2ce14b72007-07-05 23:05:31 -0500244
TsiChung Liewf6afe722007-06-18 13:50:13 -0500245 /* wait for DQS logic to relock */
246 for (i = 0; i < 0x200; i++) ;
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +0100247#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500248
249 return fout;
250}
251
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000252/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500253int get_clocks(void)
254{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255 gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
TsiChung Liewf6afe722007-06-18 13:50:13 -0500256 gd->cpu_clk = (gd->bus_clk * 3);
TsiChung Liew0c1e3252008-08-19 03:01:19 +0600257
Heiko Schocherf2850742012-10-24 13:48:22 +0200258#ifdef CONFIG_SYS_I2C_FSL
Simon Glassc2baaec2012-12-13 20:48:49 +0000259 gd->arch.i2c1_clk = gd->bus_clk;
TsiChung Liew0c1e3252008-08-19 03:01:19 +0600260#endif
261
TsiChung Liewf6afe722007-06-18 13:50:13 -0500262 return (0);
263}