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git01.mediatek.com / filogic / uboot / ba7dac39f0cfa11152cc64deb23da74cd8b82a91 / . / board / Marvell / octeon_nic23 / board_ddr.h
blob: eac877faf8533d792346b6b99b1837c97a143348 [file] [log] [blame]
Stefan Roeseede2c662021-04-07 09:12:38 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * https://spdx.org/licenses
6 */
7
8#ifndef __BOARD_DDR_H__
9#define __BOARD_DDR_H__
10
11#define OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0 \
12 { {0x0, 0x0}, {octeon_nic23_cfg0_spd_values, NULL} }
13
14#define NIC23_MTA8ATF51264AZ2G3_SPD_VALUES \
15 0x23, 0x10, 0x0c, 0x02, 0x84, 0x19, 0x00, 0x08, \
16 0x00, 0x00, 0x00, 0x03, 0x01, 0x0b, 0x80, 0x00, \
17 0x00, 0x00, 0x08, 0x0c, 0xf4, 0x1b, 0x00, 0x00, \
18 0x6c, 0x6c, 0x6c, 0x11, 0x08, 0x74, 0x20, 0x08, \
19 0x00, 0x05, 0x70, 0x03, 0x00, 0xa8, 0x1e, 0x2b, \
20 0x2b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
21 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
22 0x00, 0x00, 0x00, 0x00, 0x0c, 0x2c, 0x15, 0x35, \
23 0x15, 0x35, 0x0b, 0x2c, 0x15, 0x35, 0x0b, 0x35, \
24 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36, 0x00, 0x00, \
25 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
26 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
27 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
28 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
29 0x00, 0x00, 0x00, 0x00, 0x00, 0xec, 0xb5, 0xce, \
30 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x30, 0x0e, \
31 0x11, 0x11, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, \
32 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
33 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
34 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
35 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
36 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
37 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
38 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
39 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
40 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
41 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
42 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
43 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
44 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
45 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
46 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x2e, \
47 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
48 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
49 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
50 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
51 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
52 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
53 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
54 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
55 0x80, 0x2c, 0x0f, 0x14, 0x50, 0x0e, 0x08, 0x18, \
56 0xc8, 0x31, 0x38, 0x41, 0x53, 0x46, 0x31, 0x47, \
57 0x37, 0x32, 0x41, 0x5a, 0x2d, 0x32, 0x47, 0x31, \
58 0x41, 0x31, 0x20, 0x20, 0x20, 0x31, 0x80, 0x2c, \
59 0x41, 0x44, 0x50, 0x41, 0x45, 0x4e, 0x43, 0x39, \
60 0x30, 0x30, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, \
61 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
62 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
63 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
64 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
65 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
66 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
67 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
68 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
69 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
70 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
71 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
72 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
73 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
74 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
75 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
76 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
77 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
78 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
79
80#define OCTEON_NIC23_CFG0_SPD_VALUES NIC23_MTA8ATF51264AZ2G3_SPD_VALUES
81
82#define OCTEON_NIC23_BOARD_EEPROM_TWSI_ADDR 0x56
83
84#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT \
85{ \
86 .cn78xx = { \
87 .pasr_00 = 0, \
88 .asr_00 = 0, \
89 .srt_00 = 0, \
90 .rtt_wr_00 = ddr4_rttwr_80ohm & 3, \
91 .rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
92 .dic_00 = ddr4_dic_34ohm, \
93 .rtt_nom_00 = 0, \
94 .pasr_01 = 0, \
95 .asr_01 = 0, \
96 .srt_01 = 0, \
97 .rtt_wr_01 = 0, \
98 .dic_01 = ddr4_dic_34ohm, \
99 .rtt_nom_01 = 0, \
100 .pasr_10 = 0, \
101 .asr_10 = 0, \
102 .srt_10 = 0, \
103 .rtt_wr_10 = 0, \
104 .dic_10 = ddr4_dic_34ohm, \
105 .rtt_nom_10 = 0, \
106 .pasr_11 = 0, \
107 .asr_11 = 0, \
108 .srt_11 = 0, \
109 .rtt_wr_11 = 0, \
110 .dic_11 = ddr4_dic_34ohm, \
111 .rtt_nom_11 = 0, \
112 } \
113 }
114
115#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT \
116{ \
117 .cn78xx = { \
118 .pasr_00 = 0, \
119 .asr_00 = 0, \
120 .srt_00 = 0, \
121 .rtt_wr_00 = ddr4_rttwr_80ohm & 3, \
122 .rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
123 .dic_00 = ddr4_dic_34ohm, \
124 .rtt_nom_00 = 0, \
125 .pasr_01 = 0, \
126 .asr_01 = 0, \
127 .srt_01 = 0, \
128 .rtt_wr_01 = 0, \
129 .dic_01 = ddr4_dic_34ohm, \
130 .rtt_nom_01 = 0, \
131 .pasr_10 = 0, \
132 .asr_10 = 0, \
133 .srt_10 = 0, \
134 .rtt_wr_10 = ddr4_rttwr_80ohm & 3, \
135 .rtt_wr_10_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
136 .dic_10 = ddr4_dic_34ohm, \
137 .rtt_nom_10 = 0, \
138 .pasr_11 = 0, \
139 .asr_11 = 0, \
140 .srt_11 = 0, \
141 .rtt_wr_11 = 0, \
142 .dic_11 = ddr4_dic_34ohm, \
143 .rtt_nom_11 = 0 \
144 } \
145}
146
147#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT \
148{ \
149 .cn78xx = { \
150 .rtt_park_00 = ddr4_rttpark_60ohm, \
151 .vref_value_00 = 0x22, \
152 .vref_range_00 = 0, \
153 .rtt_park_01 = 0, \
154 .vref_value_01 = 0, \
155 .vref_range_01 = 0, \
156 .rtt_park_10 = 0, \
157 .vref_value_10 = 0, \
158 .vref_range_10 = 0, \
159 .rtt_park_11 = 0, \
160 .vref_value_11 = 0, \
161 .vref_range_11 = 0 \
162 } \
163}
164
165#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT \
166{ \
167 .cn78xx = { \
168 .rtt_park_00 = ddr4_rttpark_48ohm, \
169 .vref_value_00 = 0x1f, \
170 .vref_range_00 = 0, \
171 .rtt_park_01 = 0, \
172 .vref_value_01 = 0, \
173 .vref_range_01 = 0, \
174 .rtt_park_10 = ddr4_rttpark_48ohm, \
175 .vref_value_10 = 0x1f, \
176 .vref_range_10 = 0, \
177 .rtt_park_11 = 0, \
178 .vref_value_11 = 0, \
179 .vref_range_11 = 0 \
180 } \
181}
182
183#define OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION \
184 /* 1 */ \
185 { \
186 ddr4_dqx_driver_34_ohm, \
187 0x00000000ULL, \
188 OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT, \
189 OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT, \
190 ddr4_rodt_ctl_48_ohm, \
191 0x00000000ULL, \
192 0 \
193 }, \
194 /* 2 */ \
195 { \
196 ddr4_dqx_driver_34_ohm, \
197 0x00000000ULL, \
198 OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT, \
199 OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT, \
200 ddr4_rodt_ctl_80_ohm, \
201 0x00000000ULL, \
202 0 \
203 }
204
205/*
206 * Construct a static initializer for the ddr_configuration_t variable that
207 * holds (almost) all of the information required for DDR initialization.
208 */
209
210/*
211 * The parameters below make up the custom_lmc_config data structure.
212 * This structure is used to customize the way that the LMC DRAM
213 * Controller is configured for a particular board design.
214 *
215 * Refer to the file lib_octeon_board_table_entry.h for a description
216 * of the custom board settings. It is usually kept in the following
217 * location... arch/mips/include/asm/arch-octeon/
218 *
219 */
220
221#define OCTEON_NIC23_DDR_CONFIGURATION \
222/* Interface 0 */ \
223{ \
224 .custom_lmc_config = { \
225 .min_rtt_nom_idx = 2, \
226 .max_rtt_nom_idx = 5, \
227 .min_rodt_ctl = 2, \
228 .max_rodt_ctl = 4, \
229 .ck_ctl = ddr4_driver_34_ohm, \
230 .cmd_ctl = ddr4_driver_34_ohm, \
231 .ctl_ctl = ddr4_driver_34_ohm, \
232 .min_cas_latency = 7, \
233 .offset_en = 1, \
234 .offset_udimm = 2, \
235 .offset_rdimm = 2, \
236 .ddr_rtt_nom_auto = 0, \
237 .ddr_rodt_ctl_auto = 0, \
238 .rlevel_compute = 0, \
239 .ddr2t_udimm = 1, \
240 .ddr2t_rdimm = 1, \
241 .maximum_adjacent_rlevel_delay_increment = 2, \
242 .fprch2 = 2, \
243 .dll_write_offset = NULL, \
244 .dll_read_offset = NULL, \
245 .disable_sequential_delay_check = 1, \
246 .parity = 0 \
247 }, \
248 .dimm_config_table = { \
249 OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0, \
250 DIMM_CONFIG_TERMINATOR \
251 }, \
252 .unbuffered = { \
253 .ddr_board_delay = 0, \
254 .lmc_delay_clk = 0, \
255 .lmc_delay_cmd = 0, \
256 .lmc_delay_dq = 0 \
257 }, \
258 .registered = { \
259 .ddr_board_delay = 0, \
260 .lmc_delay_clk = 0, \
261 .lmc_delay_cmd = 0, \
262 .lmc_delay_dq = 0 \
263 }, \
264 .odt_1rank_config = { \
265 OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION \
266 }, \
267},
268
269#endif /* __BOARD_DDR_H__ */