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git01.mediatek.com / filogic / uboot / ba550f2bf2cf6d3cd66edd9e7f23d7528f9150eb / . / arch / arm / dts / sdm845.dtsi
blob: 3b86b9328fc6dd7062ed4112cf055bb32e20b4c2 [file] [log] [blame]
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Qualcomm SDM845 chip device tree source
4 *
5 * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
6 *
7 */
8
9/dts-v1/;
10
Sumit Garg8bdffc32022-07-12 12:42:06 +0530[diff] [blame]11#include <dt-bindings/clock/qcom,gcc-sdm845.h>
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]12#include "skeleton64.dtsi"
13
14/ {
15 soc: soc {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges = <0 0 0 0xffffffff>;
19 compatible = "simple-bus";
20
21 gcc: clock-controller@100000 {
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]22 compatible = "qcom,gcc-sdm845";
23 reg = <0x100000 0x1f0000>;
24 #clock-cells = <1>;
25 #reset-cells = <1>;
26 #power-domain-cells = <1>;
27 };
28
29 gpio_north: gpio_north@3900000 {
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]30 #gpio-cells = <2>;
31 compatible = "qcom,sdm845-pinctrl";
32 reg = <0x3900000 0x400000>;
33 gpio-count = <150>;
34 gpio-controller;
35 gpio-ranges = <&gpio_north 0 0 150>;
36 gpio-bank-name = "soc_north.";
37 };
38
39 tlmm_north: pinctrl_north@3900000 {
Sumit Gargb7572e52022-07-27 13:52:04 +0530[diff] [blame]40 compatible = "qcom,sdm845-pinctrl";
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]41 reg = <0x3900000 0x400000>;
42 gpio-count = <150>;
43 gpio-controller;
44 #gpio-cells = <2>;
45 gpio-ranges = <&tlmm_north 0 0 150>;
46
47 /* DEBUG UART */
48 qup_uart9: qup-uart9-default {
Dzmitry Sankouski8e3bdd52022-02-22 21:49:53 +0300[diff] [blame]49 pins = "GPIO_4", "GPIO_5";
Sumit Garg60b78042022-07-12 12:42:07 +0530[diff] [blame]50 function = "qup9";
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]51 };
52 };
53
Vladimir Zapolskiy5c5e8d42023-04-21 20:50:41 +0300[diff] [blame]54 qupv3_id_1: geniqup@ac0000 {
55 compatible = "qcom,geni-se-qup";
56 reg = <0x00ac0000 0x6000>;
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60
61 uart9: serial@a84000 {
62 compatible = "qcom,geni-debug-uart";
63 reg = <0xa84000 0x4000>;
64 clock-names = "se";
65 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&qup_uart9>;
68 };
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]69 };
70
71 spmi@c440000 {
72 compatible = "qcom,spmi-pmic-arb";
73 reg = <0xc440000 0x1100>,
74 <0xc600000 0x2000000>,
75 <0xe600000 0x100000>;
76 reg-names = "cnfg", "core", "obsrvr";
77 #address-cells = <0x1>;
78 #size-cells = <0x1>;
79
80 qcom,revid@100 {
81 compatible = "qcom,qpnp-revid";
82 reg = <0x100 0x100>;
83 };
84
85 pmic0: pm8998@0 {
86 compatible = "qcom,spmi-pmic";
87 reg = <0x0 0x1>;
88 #address-cells = <0x1>;
89 #size-cells = <0x1>;
90
91 pm8998_pon: pm8998_pon@800 {
92 compatible = "qcom,pm8998-pwrkey";
93 reg = <0x800 0x100>;
94 #gpio-cells = <2>;
95 gpio-controller;
96 gpio-bank-name = "pm8998_key.";
97 };
98
99 pm8998_gpios: pm8998_gpios@c000 {
100 compatible = "qcom,pm8998-gpio";
101 reg = <0xc000 0x1a00>;
102 gpio-controller;
103 gpio-count = <21>;
104 #gpio-cells = <2>;
105 gpio-bank-name = "pm8998.";
106 };
107 };
108
109 pmic1: pm8998@1 {
110 compatible = "qcom,spmi-pmic";
111 reg = <0x1 0x0>;
112 #address-cells = <0x2>;
113 #size-cells = <0x0>;
114 };
115 };
116 };
117};