| Rajeshwari Shinde | ba3b893 | 2012-11-02 01:15:36 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2012 SAMSUNG Electronics |
| 3 | * Padmavathi Venna <padma.v@samsung.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_ |
| 21 | #define __ASM_ARCH_EXYNOS_COMMON_SPI_H_ |
| 22 | |
| 23 | #ifndef __ASSEMBLY__ |
| 24 | |
| 25 | /* SPI peripheral register map; padded to 64KB */ |
| 26 | struct exynos_spi { |
| 27 | unsigned int ch_cfg; /* 0x00 */ |
| 28 | unsigned char reserved0[4]; |
| 29 | unsigned int mode_cfg; /* 0x08 */ |
| 30 | unsigned int cs_reg; /* 0x0c */ |
| 31 | unsigned char reserved1[4]; |
| 32 | unsigned int spi_sts; /* 0x14 */ |
| 33 | unsigned int tx_data; /* 0x18 */ |
| 34 | unsigned int rx_data; /* 0x1c */ |
| 35 | unsigned int pkt_cnt; /* 0x20 */ |
| 36 | unsigned char reserved2[4]; |
| 37 | unsigned char reserved3[4]; |
| 38 | unsigned int fb_clk; /* 0x2c */ |
| 39 | unsigned char padding[0xffd0]; |
| 40 | }; |
| 41 | |
| 42 | #define EXYNOS_SPI_MAX_FREQ 50000000 |
| 43 | |
| 44 | #define SPI_TIMEOUT_MS 10 |
| 45 | |
| 46 | /* SPI_CHCFG */ |
| 47 | #define SPI_CH_HS_EN (1 << 6) |
| 48 | #define SPI_CH_RST (1 << 5) |
| 49 | #define SPI_SLAVE_MODE (1 << 4) |
| 50 | #define SPI_CH_CPOL_L (1 << 3) |
| 51 | #define SPI_CH_CPHA_B (1 << 2) |
| 52 | #define SPI_RX_CH_ON (1 << 1) |
| 53 | #define SPI_TX_CH_ON (1 << 0) |
| 54 | |
| 55 | /* SPI_MODECFG */ |
| 56 | #define SPI_MODE_CH_WIDTH_WORD (0x2 << 29) |
| 57 | #define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17) |
| 58 | |
| 59 | /* SPI_CSREG */ |
| 60 | #define SPI_SLAVE_SIG_INACT (1 << 0) |
| 61 | |
| 62 | /* SPI_STS */ |
| 63 | #define SPI_ST_TX_DONE (1 << 25) |
| 64 | #define SPI_FIFO_LVL_MASK 0x1ff |
| 65 | #define SPI_TX_LVL_OFFSET 6 |
| 66 | #define SPI_RX_LVL_OFFSET 15 |
| 67 | |
| 68 | /* Feedback Delay */ |
| 69 | #define SPI_CLK_BYPASS (0 << 0) |
| 70 | #define SPI_FB_DELAY_90 (1 << 0) |
| 71 | #define SPI_FB_DELAY_180 (2 << 0) |
| 72 | #define SPI_FB_DELAY_270 (3 << 0) |
| 73 | |
| 74 | /* Packet Count */ |
| 75 | #define SPI_PACKET_CNT_EN (1 << 16) |
| 76 | |
| 77 | #endif /* __ASSEMBLY__ */ |
| 78 | #endif |