Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl |
| 3 | * |
| 4 | * Configuation settings for the TI OMAP NetStar board. |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #ifndef __CONFIG_H |
| 26 | #define __CONFIG_H |
| 27 | |
| 28 | #include <configs/omap1510.h> |
| 29 | |
| 30 | /* |
| 31 | * High Level Configuration Options |
| 32 | * (easy to change) |
| 33 | */ |
| 34 | #define CONFIG_ARM925T 1 /* This is an arm925t CPU */ |
| 35 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
| 36 | #define CONFIG_OMAP1510 1 /* which is in a 5910 */ |
| 37 | |
| 38 | /* Input clock of PLL */ |
| 39 | #define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */ |
| 40 | #define CONFIG_XTAL_FREQ 12000000 |
| 41 | |
| 42 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
| 43 | |
| 44 | #define CONFIG_MISC_INIT_R /* There is nothing to really init */ |
| 45 | #define BOARD_LATE_INIT /* but we flash the LEDs here */ |
| 46 | |
| 47 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
| 48 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
| 49 | #define CONFIG_INITRD_TAG 1 |
| 50 | |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 51 | #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | #define CONFIG_SYS_CONSOLE_INFO_QUIET |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 53 | |
| 54 | /* |
| 55 | * Physical Memory Map |
| 56 | */ |
| 57 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
| 58 | #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
Peter Pearse | 1b079e0 | 2008-02-01 16:49:08 +0000 | [diff] [blame] | 59 | #define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 60 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
| 61 | |
| 62 | /* |
| 63 | * FLASH organization |
| 64 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 65 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
| 66 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
Peter Pearse | 1b079e0 | 2008-02-01 16:49:08 +0000 | [diff] [blame] | 67 | #define PHYS_FLASH_1_SIZE (1 * 1024 * 1024) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 68 | #define CONFIG_SYS_MAX_FLASH_SECT 19 |
| 69 | #define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* in ticks */ |
| 70 | #define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 71 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 72 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
| 73 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 74 | |
| 75 | /* |
| 76 | * Environment settings |
| 77 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 78 | #define CONFIG_ENV_IS_IN_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 79 | #define CONFIG_ENV_ADDR 0x4000 |
| 80 | #define CONFIG_ENV_SIZE (8 * 1024) |
| 81 | #define CONFIG_ENV_SECT_SIZE (8 * 1024) |
| 82 | #define CONFIG_ENV_ADDR_REDUND 0x6000 |
| 83 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 84 | #define CONFIG_ENV_OVERWRITE |
| 85 | |
| 86 | /* |
| 87 | * Size of malloc() pool |
| 88 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| 90 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 91 | |
| 92 | /* |
| 93 | * The stack size is set up in start.S using the settings below |
| 94 | */ |
Peter Pearse | 1b079e0 | 2008-02-01 16:49:08 +0000 | [diff] [blame] | 95 | #define CONFIG_STACKSIZE (1 * 1024 * 1024) /* regular stack */ |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 96 | |
| 97 | /* |
| 98 | * Hardware drivers |
| 99 | */ |
| 100 | #define CONFIG_DRIVER_SMC91111 |
| 101 | #define CONFIG_SMC91111_BASE 0x04000300 |
| 102 | |
| 103 | /* |
| 104 | * NS16550 Configuration |
| 105 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 106 | #define CONFIG_SYS_NS16550 |
| 107 | #define CONFIG_SYS_NS16550_SERIAL |
| 108 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 109 | #define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ |
| 110 | #define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 111 | |
| 112 | #define CONFIG_CONS_INDEX 1 |
| 113 | #define CONFIG_BAUDRATE 115200 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 114 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 115 | |
| 116 | /*#define CONFIG_SKIP_RELOCATE_UBOOT*/ |
| 117 | /*#define CONFIG_SKIP_LOWLEVEL_INIT */ |
| 118 | |
| 119 | /* |
| 120 | * NAND flash |
| 121 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 122 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Bartlomiej Sieka | 582f1a3 | 2006-03-05 18:57:33 +0100 | [diff] [blame] | 123 | #define NAND_MAX_CHIPS 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 124 | #define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23) |
Peter Pearse | 1b079e0 | 2008-02-01 16:49:08 +0000 | [diff] [blame] | 125 | #define NAND_ALLOW_ERASE_ALL 1 |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 126 | |
| 127 | /* |
Peter Pearse | 1b079e0 | 2008-02-01 16:49:08 +0000 | [diff] [blame] | 128 | * partitions (mtdparts command line support) |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 129 | */ |
| 130 | #define CONFIG_JFFS2_CMDLINE |
| 131 | #define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0" |
Peter Pearse | 1b079e0 | 2008-02-01 16:49:08 +0000 | [diff] [blame] | 132 | #define MTDPARTS_DEFAULT "mtdparts=" \ |
| 133 | "omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \ |
| 134 | "omapnand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)" |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 135 | |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 136 | |
Jon Loeliger | 74fdb63 | 2007-07-04 22:33:07 -0500 | [diff] [blame] | 137 | /* |
| 138 | * Command line configuration. |
| 139 | */ |
| 140 | |
| 141 | #define CONFIG_CMD_BDI |
| 142 | #define CONFIG_CMD_BOOTD |
| 143 | #define CONFIG_CMD_DHCP |
| 144 | #define CONFIG_CMD_ENV |
| 145 | #define CONFIG_CMD_FLASH |
| 146 | #define CONFIG_CMD_IMI |
| 147 | #define CONFIG_CMD_JFFS2 |
| 148 | #define CONFIG_CMD_LOADB |
| 149 | #define CONFIG_CMD_MEMORY |
| 150 | #define CONFIG_CMD_NAND |
| 151 | #define CONFIG_CMD_NET |
| 152 | #define CONFIG_CMD_PING |
| 153 | #define CONFIG_CMD_RUN |
| 154 | |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 155 | |
| 156 | #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 157 | |
Jon Loeliger | c6d535a | 2007-07-09 21:57:31 -0500 | [diff] [blame] | 158 | /* |
| 159 | * BOOTP options |
| 160 | */ |
| 161 | #define CONFIG_BOOTP_SUBNETMASK |
| 162 | #define CONFIG_BOOTP_GATEWAY |
| 163 | #define CONFIG_BOOTP_HOSTNAME |
| 164 | #define CONFIG_BOOTP_BOOTPATH |
| 165 | |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 166 | #define CONFIG_LOOPW |
| 167 | |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 168 | #define CONFIG_BOOTDELAY 3 |
| 169 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ |
| 170 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 171 | #define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ |
Peter Pearse | 1b079e0 | 2008-02-01 16:49:08 +0000 | [diff] [blame] | 172 | #define CONFIG_BOOTCOMMAND "run fboot" |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 173 | #define CONFIG_PREBOOT "run setup" |
Peter Pearse | 1b079e0 | 2008-02-01 16:49:08 +0000 | [diff] [blame] | 174 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 175 | "autostart=yes\0" \ |
| 176 | "ospart=0\0" \ |
| 177 | "setup=setenv bootargs console=ttyS0,$baudrate " \ |
| 178 | "$mtdparts\0" \ |
| 179 | "setpart=" \ |
| 180 | "if test -n $swapos; then " \ |
| 181 | "setenv swapos; saveenv; " \ |
| 182 | "else " \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 183 | "if test $ospart -eq 0; then setenv ospart 1;" \ |
| 184 | "else setenv ospart 0; fi; " \ |
Peter Pearse | 1b079e0 | 2008-02-01 16:49:08 +0000 | [diff] [blame] | 185 | "fi\0" \ |
| 186 | "nfsargs=setenv bootargs $bootargs " \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 187 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ |
Peter Pearse | 1b079e0 | 2008-02-01 16:49:08 +0000 | [diff] [blame] | 188 | "nfsroot=$rootpath root=/dev/nfs\0" \ |
| 189 | "flashargs=run setpart;setenv bootargs $bootargs " \ |
| 190 | "root=mtd:rootfs$ospart ro " \ |
| 191 | "rootfstype=jffs2\0" \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 192 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ |
Peter Pearse | 1b079e0 | 2008-02-01 16:49:08 +0000 | [diff] [blame] | 193 | "fboot=run flashargs;nboot kernel$ospart\0" \ |
| 194 | "nboot=bootp;run nfsargs;tftp\0" |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 195 | |
| 196 | #if 0 /* feel free to disable for development */ |
| 197 | #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ |
Stefan Roese | 3762825 | 2008-08-06 14:05:38 +0200 | [diff] [blame] | 198 | #define CONFIG_AUTOBOOT_PROMPT \ |
| 199 | "\nNetStar PBX - boot in %d secs...\n", bootdelay |
Peter Pearse | 1b079e0 | 2008-02-01 16:49:08 +0000 | [diff] [blame] | 200 | #define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */ |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 201 | #endif |
| 202 | |
| 203 | /* |
| 204 | * Miscellaneous configurable options |
| 205 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 206 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 207 | #define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */ |
| 208 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 209 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 210 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 211 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 212 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 213 | #define CONFIG_SYS_HUSH_PARSER |
| 214 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 215 | #define CONFIG_AUTO_COMPLETE |
| 216 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 217 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 |
| 218 | #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \ |
| 219 | (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE) |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 220 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 221 | #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 222 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 224 | |
| 225 | /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. |
| 226 | * This time is further subdivided by a local divisor. |
| 227 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 228 | #define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE |
| 229 | #define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */ |
| 230 | #define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) |
Wolfgang Denk | 7b9bc3a | 2005-09-14 23:53:32 +0200 | [diff] [blame] | 231 | |
| 232 | #define OMAP5910_DPLL_DIV 1 |
| 233 | #define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ |
| 234 | (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) |
| 235 | |
| 236 | #define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ |
| 237 | #define OMAP5910_LCD_DIV 2 /* CKL/4 */ |
| 238 | #define OMAP5910_ARM_DIV 0 /* CKL/1 */ |
| 239 | #define OMAP5910_DSP_DIV 0 /* CKL/1 */ |
| 240 | #define OMAP5910_TC_DIV 1 /* CKL/2 */ |
| 241 | #define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ |
| 242 | #define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ |
| 243 | |
| 244 | #define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */ |
| 245 | #define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ |
| 246 | (OMAP5910_LCD_DIV << 2) | \ |
| 247 | (OMAP5910_ARM_DIV << 4) | \ |
| 248 | (OMAP5910_DSP_DIV << 6) | \ |
| 249 | (OMAP5910_TC_DIV << 8) | \ |
| 250 | (OMAP5910_DSP_MMU_DIV << 10) | \ |
| 251 | (OMAP5910_ARM_TIM_SEL << 12)) |
| 252 | |
| 253 | #endif /* __CONFIG_H */ |