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git01.mediatek.com / filogic / uboot / b98e892d148ed9f776c3c01b9387a3c9075e414f / . / drivers / clk / sunxi / clk_r40.c
blob: b9457e19714a005c43c76412aecda9a2197a993a [file] [log] [blame]
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun8i-r40-ccu.h>
13#include <dt-bindings/reset/sun8i-r40-ccu.h>
14
15static struct ccu_clk_gate r40_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]20 [CLK_BUS_OTG] = GATE(0x060, BIT(25)),
21 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
22 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
23 [CLK_BUS_EHCI2] = GATE(0x060, BIT(28)),
24 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
25 [CLK_BUS_OHCI1] = GATE(0x060, BIT(30)),
26 [CLK_BUS_OHCI2] = GATE(0x060, BIT(31)),
27
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]28 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
29 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
30 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
31 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
32 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
33 [CLK_BUS_UART5] = GATE(0x06c, BIT(21)),
34 [CLK_BUS_UART6] = GATE(0x06c, BIT(22)),
35 [CLK_BUS_UART7] = GATE(0x06c, BIT(23)),
36
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]37 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
38 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
39 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
40 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
41 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
42 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
43};
44
45static struct ccu_reset r40_resets[] = {
46 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
47 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
48 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
49
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]50 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
51 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
52 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
53 [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]54 [RST_BUS_OTG] = RESET(0x2c0, BIT(25)),
55 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
56 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
57 [RST_BUS_EHCI2] = RESET(0x2c0, BIT(28)),
58 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
59 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)),
60 [RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]61
62 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
63 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
64 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
65 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
66 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
67 [RST_BUS_UART5] = RESET(0x2d8, BIT(21)),
68 [RST_BUS_UART6] = RESET(0x2d8, BIT(22)),
69 [RST_BUS_UART7] = RESET(0x2d8, BIT(23)),
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]70};
71
72static const struct ccu_desc r40_ccu_desc = {
73 .gates = r40_gates,
74 .resets = r40_resets,
75};
76
77static int r40_clk_bind(struct udevice *dev)
78{
79 return sunxi_reset_bind(dev, ARRAY_SIZE(r40_resets));
80}
81
82static const struct udevice_id r40_clk_ids[] = {
83 { .compatible = "allwinner,sun8i-r40-ccu",
84 .data = (ulong)&r40_ccu_desc },
85 { }
86};
87
88U_BOOT_DRIVER(clk_sun8i_r40) = {
89 .name = "sun8i_r40_ccu",
90 .id = UCLASS_CLK,
91 .of_match = r40_clk_ids,
92 .priv_auto_alloc_size = sizeof(struct ccu_priv),
93 .ops = &sunxi_clk_ops,
94 .probe = sunxi_clk_probe,
95 .bind = r40_clk_bind,
96};