| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Configuration settings for the Renesas GRPEACH board |
| 4 | * |
| 5 | * Copyright (C) 2017-2019 Renesas Electronics |
| 6 | */ |
| 7 | |
| 8 | #ifndef __GRPEACH_H |
| 9 | #define __GRPEACH_H |
| 10 | |
| 11 | /* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ |
| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 12 | |
| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 13 | /* Miscellaneous */ |
| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 14 | |
| 15 | /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 16 | #define CFG_SYS_SDRAM_BASE 0x20000000 |
| 17 | #define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) |
| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 18 | |
| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 19 | /* Network interface */ |
| 20 | #define CONFIG_SH_ETHER_USE_PORT 0 |
| 21 | #define CONFIG_SH_ETHER_PHY_ADDR 0 |
| 22 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII |
| 23 | #define CONFIG_SH_ETHER_CACHE_WRITEBACK |
| 24 | #define CONFIG_SH_ETHER_CACHE_INVALIDATE |
| 25 | #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 |
| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 26 | |
| 27 | #endif /* __GRPEACH_H */ |