| Phil Edworthy | 04a6275 | 2012-05-15 22:15:51 +0000 | [diff] [blame] | 1 | #ifndef _ASM_CPU_SH7269_H_ |
| 2 | #define _ASM_CPU_SH7269_H_ |
| 3 | |
| 4 | /* Cache */ |
| 5 | #define CCR1 0xFFFC1000 |
| 6 | #define CCR CCR1 |
| 7 | |
| 8 | /* SCIF */ |
| 9 | #define SCSMR_0 0xE8007000 |
| 10 | #define SCIF0_BASE SCSMR_0 |
| 11 | #define SCSMR_1 0xE8007800 |
| 12 | #define SCIF1_BASE SCSMR_1 |
| 13 | #define SCSMR_2 0xE8008000 |
| 14 | #define SCIF2_BASE SCSMR_2 |
| 15 | #define SCSMR_3 0xE8008800 |
| 16 | #define SCIF3_BASE SCSMR_3 |
| 17 | #define SCSMR_7 0xE800A800 |
| 18 | #define SCIF7_BASE SCSMR_7 |
| 19 | |
| 20 | /* Timer(CMT) */ |
| 21 | #define CMSTR 0xFFFEC000 |
| 22 | #define CMCSR_0 0xFFFEC002 |
| 23 | #define CMCNT_0 0xFFFEC004 |
| 24 | #define CMCOR_0 0xFFFEC006 |
| 25 | |
| 26 | #endif /* _ASM_CPU_SH7269_H_ */ |