blob: 338b08bd77005f0b477ad594ce1c37d588943bf2 [file] [log] [blame]
wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
Stefan Roeseeff3a0a2007-10-31 17:55:58 +010025#include <asm/cache.h>
Yuri Tikhonov18db5a62008-04-29 13:32:45 +020026#include <watchdog.h>
wdenk359733b2003-03-31 17:27:09 +000027
Dave Liu06ed90b2008-12-05 15:36:14 +080028void flush_cache(ulong start_addr, ulong size)
wdenkaffae2b2002-08-17 09:36:01 +000029{
wdenk359733b2003-03-31 17:27:09 +000030#ifndef CONFIG_5xx
Dave Liu06ed90b2008-12-05 15:36:14 +080031 ulong addr, start, end;
wdenkaffae2b2002-08-17 09:36:01 +000032
Dave Liu06ed90b2008-12-05 15:36:14 +080033 start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
34 end = start_addr + size - 1;
wdenkaffae2b2002-08-17 09:36:01 +000035
Kumar Gala3b967ae2009-02-06 08:08:06 -060036 for (addr = start; (addr <= end) && (addr >= start);
37 addr += CONFIG_SYS_CACHELINE_SIZE) {
Dave Liu06ed90b2008-12-05 15:36:14 +080038 asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
39 WATCHDOG_RESET();
40 }
41 /* wait for all dcbst to complete on bus */
42 asm volatile("sync" : : : "memory");
43
Kumar Gala3b967ae2009-02-06 08:08:06 -060044 for (addr = start; (addr <= end) && (addr >= start);
45 addr += CONFIG_SYS_CACHELINE_SIZE) {
Dave Liu06ed90b2008-12-05 15:36:14 +080046 asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
47 WATCHDOG_RESET();
wdenkaffae2b2002-08-17 09:36:01 +000048 }
Dave Liu06ed90b2008-12-05 15:36:14 +080049 asm volatile("sync" : : : "memory");
50 /* flush prefetch queue */
51 asm volatile("isync" : : : "memory");
wdenk359733b2003-03-31 17:27:09 +000052#endif
wdenkaffae2b2002-08-17 09:36:01 +000053}