Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2019 Google LLC |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <dm.h> |
| 8 | #include <log.h> |
| 9 | #include <tpm_api.h> |
| 10 | #include <tpm-v1.h> |
| 11 | #include <tpm-v2.h> |
| 12 | #include <tpm_api.h> |
| 13 | |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 14 | u32 tpm_startup(struct udevice *dev, enum tpm_startup_type mode) |
| 15 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 16 | if (tpm_is_v1(dev)) { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 17 | return tpm1_startup(dev, mode); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 18 | } else if (tpm_is_v2(dev)) { |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 19 | enum tpm2_startup_types type; |
| 20 | |
| 21 | switch (mode) { |
| 22 | case TPM_ST_CLEAR: |
| 23 | type = TPM2_SU_CLEAR; |
| 24 | break; |
| 25 | case TPM_ST_STATE: |
| 26 | type = TPM2_SU_STATE; |
| 27 | break; |
| 28 | default: |
| 29 | case TPM_ST_DEACTIVATED: |
| 30 | return -EINVAL; |
| 31 | } |
| 32 | return tpm2_startup(dev, type); |
| 33 | } else { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 34 | return -ENOSYS; |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 35 | } |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 36 | } |
| 37 | |
Ilias Apalodimas | 42d7bdf | 2023-01-25 12:18:36 +0200 | [diff] [blame] | 38 | u32 tpm_auto_start(struct udevice *dev) |
| 39 | { |
Simon Glass | 3467ed2 | 2023-02-21 06:24:52 -0700 | [diff] [blame] | 40 | u32 rc; |
Ilias Apalodimas | 42d7bdf | 2023-01-25 12:18:36 +0200 | [diff] [blame] | 41 | |
Simon Glass | 3467ed2 | 2023-02-21 06:24:52 -0700 | [diff] [blame] | 42 | /* |
| 43 | * the tpm_init() will return -EBUSY if the init has already happened |
| 44 | * The selftest and startup code can run multiple times with no side |
| 45 | * effects |
| 46 | */ |
| 47 | rc = tpm_init(dev); |
| 48 | if (rc && rc != -EBUSY) |
| 49 | return rc; |
| 50 | |
| 51 | if (tpm_is_v1(dev)) |
| 52 | return tpm1_auto_start(dev); |
| 53 | else if (tpm_is_v2(dev)) |
| 54 | return tpm2_auto_start(dev); |
| 55 | else |
| 56 | return -ENOSYS; |
Ilias Apalodimas | 42d7bdf | 2023-01-25 12:18:36 +0200 | [diff] [blame] | 57 | } |
| 58 | |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 59 | u32 tpm_resume(struct udevice *dev) |
| 60 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 61 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 62 | return tpm1_startup(dev, TPM_ST_STATE); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 63 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 64 | return tpm2_startup(dev, TPM2_SU_STATE); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 65 | else |
| 66 | return -ENOSYS; |
| 67 | } |
| 68 | |
| 69 | u32 tpm_self_test_full(struct udevice *dev) |
| 70 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 71 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 72 | return tpm1_self_test_full(dev); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 73 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 74 | return tpm2_self_test(dev, TPMI_YES); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 75 | else |
| 76 | return -ENOSYS; |
| 77 | } |
| 78 | |
| 79 | u32 tpm_continue_self_test(struct udevice *dev) |
| 80 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 81 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 82 | return tpm1_continue_self_test(dev); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 83 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 84 | return tpm2_self_test(dev, TPMI_NO); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 85 | else |
| 86 | return -ENOSYS; |
| 87 | } |
| 88 | |
| 89 | u32 tpm_clear_and_reenable(struct udevice *dev) |
| 90 | { |
| 91 | u32 ret; |
| 92 | |
| 93 | log_info("TPM: Clear and re-enable\n"); |
| 94 | ret = tpm_force_clear(dev); |
| 95 | if (ret != TPM_SUCCESS) { |
| 96 | log_err("Can't initiate a force clear\n"); |
| 97 | return ret; |
| 98 | } |
| 99 | |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 100 | if (tpm_is_v1(dev)) { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 101 | ret = tpm1_physical_enable(dev); |
| 102 | if (ret != TPM_SUCCESS) { |
| 103 | log_err("TPM: Can't set enabled state\n"); |
| 104 | return ret; |
| 105 | } |
| 106 | |
| 107 | ret = tpm1_physical_set_deactivated(dev, 0); |
| 108 | if (ret != TPM_SUCCESS) { |
| 109 | log_err("TPM: Can't set deactivated state\n"); |
| 110 | return ret; |
| 111 | } |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 112 | } |
| 113 | |
| 114 | return TPM_SUCCESS; |
| 115 | } |
| 116 | |
| 117 | u32 tpm_nv_enable_locking(struct udevice *dev) |
| 118 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 119 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 120 | return tpm1_nv_define_space(dev, TPM_NV_INDEX_LOCK, 0, 0); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 121 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 122 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 123 | else |
| 124 | return -ENOSYS; |
| 125 | } |
| 126 | |
| 127 | u32 tpm_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count) |
| 128 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 129 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 130 | return tpm1_nv_read_value(dev, index, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 131 | else if (tpm_is_v2(dev)) |
Simon Glass | 3d930ed | 2021-02-06 14:23:40 -0700 | [diff] [blame] | 132 | return tpm2_nv_read_value(dev, index, data, count); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 133 | else |
| 134 | return -ENOSYS; |
| 135 | } |
| 136 | |
| 137 | u32 tpm_nv_write_value(struct udevice *dev, u32 index, const void *data, |
| 138 | u32 count) |
| 139 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 140 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 141 | return tpm1_nv_write_value(dev, index, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 142 | else if (tpm_is_v2(dev)) |
Simon Glass | 3d930ed | 2021-02-06 14:23:40 -0700 | [diff] [blame] | 143 | return tpm2_nv_write_value(dev, index, data, count); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 144 | else |
| 145 | return -ENOSYS; |
| 146 | } |
| 147 | |
| 148 | u32 tpm_set_global_lock(struct udevice *dev) |
| 149 | { |
| 150 | return tpm_nv_write_value(dev, TPM_NV_INDEX_0, NULL, 0); |
| 151 | } |
| 152 | |
| 153 | u32 tpm_write_lock(struct udevice *dev, u32 index) |
| 154 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 155 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 156 | return -ENOSYS; |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 157 | else if (tpm_is_v2(dev)) |
Simon Glass | e9d3d59 | 2021-02-06 14:23:41 -0700 | [diff] [blame] | 158 | return tpm2_write_lock(dev, index); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 159 | else |
| 160 | return -ENOSYS; |
| 161 | } |
| 162 | |
| 163 | u32 tpm_pcr_extend(struct udevice *dev, u32 index, const void *in_digest, |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 164 | uint size, void *out_digest, const char *name) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 165 | { |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 166 | if (tpm_is_v1(dev)) { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 167 | return tpm1_extend(dev, index, in_digest, out_digest); |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 168 | } else if (tpm_is_v2(dev)) { |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 169 | return tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, in_digest, |
| 170 | TPM2_DIGEST_LEN); |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 171 | /* @name is ignored as we do not support the TPM log here */ |
| 172 | } else { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 173 | return -ENOSYS; |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 174 | } |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | u32 tpm_pcr_read(struct udevice *dev, u32 index, void *data, size_t count) |
| 178 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 179 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 180 | return tpm1_pcr_read(dev, index, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 181 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 182 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 183 | else |
| 184 | return -ENOSYS; |
| 185 | } |
| 186 | |
| 187 | u32 tpm_tsc_physical_presence(struct udevice *dev, u16 presence) |
| 188 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 189 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 190 | return tpm1_tsc_physical_presence(dev, presence); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 191 | |
| 192 | /* |
| 193 | * Nothing to do on TPM2 for this; use platform hierarchy availability |
| 194 | * instead. |
| 195 | */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 196 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 197 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 198 | else |
| 199 | return -ENOSYS; |
| 200 | } |
| 201 | |
| 202 | u32 tpm_finalise_physical_presence(struct udevice *dev) |
| 203 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 204 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 205 | return tpm1_finalise_physical_presence(dev); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 206 | |
| 207 | /* Nothing needs to be done with tpm2 */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 208 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 209 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 210 | else |
| 211 | return -ENOSYS; |
| 212 | } |
| 213 | |
| 214 | u32 tpm_read_pubek(struct udevice *dev, void *data, size_t count) |
| 215 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 216 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 217 | return tpm1_read_pubek(dev, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 218 | else if (tpm_is_v2(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 219 | return -ENOSYS; /* not implemented yet */ |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 220 | else |
| 221 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 222 | } |
| 223 | |
| 224 | u32 tpm_force_clear(struct udevice *dev) |
| 225 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 226 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 227 | return tpm1_force_clear(dev); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 228 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 229 | return tpm2_clear(dev, TPM2_RH_PLATFORM, NULL, 0); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 230 | else |
| 231 | return -ENOSYS; |
| 232 | } |
| 233 | |
| 234 | u32 tpm_physical_enable(struct udevice *dev) |
| 235 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 236 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 237 | return tpm1_physical_enable(dev); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 238 | |
| 239 | /* Nothing needs to be done with tpm2 */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 240 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 241 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 242 | else |
| 243 | return -ENOSYS; |
| 244 | } |
| 245 | |
| 246 | u32 tpm_physical_disable(struct udevice *dev) |
| 247 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 248 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 249 | return tpm1_physical_disable(dev); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 250 | |
| 251 | /* Nothing needs to be done with tpm2 */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 252 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 253 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 254 | else |
| 255 | return -ENOSYS; |
| 256 | } |
| 257 | |
| 258 | u32 tpm_physical_set_deactivated(struct udevice *dev, u8 state) |
| 259 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 260 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 261 | return tpm1_physical_set_deactivated(dev, state); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 262 | /* Nothing needs to be done with tpm2 */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 263 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 264 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 265 | else |
| 266 | return -ENOSYS; |
| 267 | } |
| 268 | |
| 269 | u32 tpm_get_capability(struct udevice *dev, u32 cap_area, u32 sub_cap, |
| 270 | void *cap, size_t count) |
| 271 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 272 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 273 | return tpm1_get_capability(dev, cap_area, sub_cap, cap, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 274 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 275 | return tpm2_get_capability(dev, cap_area, sub_cap, cap, count); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 276 | else |
| 277 | return -ENOSYS; |
| 278 | } |
| 279 | |
| 280 | u32 tpm_get_permissions(struct udevice *dev, u32 index, u32 *perm) |
| 281 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 282 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 283 | return tpm1_get_permissions(dev, index, perm); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 284 | else if (tpm_is_v2(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 285 | return -ENOSYS; /* not implemented yet */ |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 286 | else |
| 287 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 288 | } |
| 289 | |
| 290 | u32 tpm_get_random(struct udevice *dev, void *data, u32 count) |
| 291 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 292 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 293 | return tpm1_get_random(dev, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 294 | else if (tpm_is_v2(dev)) |
Sughosh Ganu | 9737fab | 2022-07-22 21:32:04 +0530 | [diff] [blame] | 295 | return tpm2_get_random(dev, data, count); |
| 296 | |
| 297 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 298 | } |