wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 1 | /* |
Graeme Russ | 45fc1d8 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 2 | * (C) Copyright 2008-2011 |
| 3 | * Graeme Russ, <graeme.russ@gmail.com> |
| 4 | * |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 5 | * (C) Copyright 2002 |
Albert ARIBAUD | 60fbc8d | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 6 | * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 7 | * |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 8 | * (C) Copyright 2002 |
| 9 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 10 | * Marius Groeger <mgroeger@sysgo.de> |
| 11 | * |
| 12 | * (C) Copyright 2002 |
| 13 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 14 | * Alex Zuepke <azu@sysgo.de> |
| 15 | * |
Bin Meng | 035c1d2 | 2014-11-09 22:18:56 +0800 | [diff] [blame] | 16 | * Part of this file is adapted from coreboot |
| 17 | * src/arch/x86/lib/cpu.c |
| 18 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 19 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 20 | */ |
| 21 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 22 | #include <common.h> |
| 23 | #include <command.h> |
Bin Meng | f967f9a | 2015-06-17 11:15:36 +0800 | [diff] [blame] | 24 | #include <dm.h> |
Simon Glass | 463fac2 | 2014-10-10 08:21:55 -0600 | [diff] [blame] | 25 | #include <errno.h> |
| 26 | #include <malloc.h> |
Bin Meng | a455964 | 2016-06-08 05:07:38 -0700 | [diff] [blame] | 27 | #include <syscon.h> |
Bin Meng | ef61f77 | 2017-04-21 07:24:32 -0700 | [diff] [blame] | 28 | #include <asm/acpi_s3.h> |
Bin Meng | 710d215 | 2017-04-21 07:24:37 -0700 | [diff] [blame] | 29 | #include <asm/acpi_table.h> |
Stefan Reinauer | 2acf848 | 2012-12-02 04:49:50 +0000 | [diff] [blame] | 30 | #include <asm/control_regs.h> |
Bin Meng | 1c9da37 | 2016-05-11 07:45:01 -0700 | [diff] [blame] | 31 | #include <asm/coreboot_tables.h> |
Simon Glass | 463fac2 | 2014-10-10 08:21:55 -0600 | [diff] [blame] | 32 | #include <asm/cpu.h> |
Bin Meng | f967f9a | 2015-06-17 11:15:36 +0800 | [diff] [blame] | 33 | #include <asm/lapic.h> |
Simon Glass | 8dda587 | 2016-03-11 22:07:11 -0700 | [diff] [blame] | 34 | #include <asm/microcode.h> |
Bin Meng | f967f9a | 2015-06-17 11:15:36 +0800 | [diff] [blame] | 35 | #include <asm/mp.h> |
Bin Meng | 1141fcf | 2016-05-11 07:45:00 -0700 | [diff] [blame] | 36 | #include <asm/mrccache.h> |
Bin Meng | c45a93b | 2015-07-06 16:31:30 +0800 | [diff] [blame] | 37 | #include <asm/msr.h> |
| 38 | #include <asm/mtrr.h> |
Simon Glass | 9f0afe7 | 2014-11-12 22:42:26 -0700 | [diff] [blame] | 39 | #include <asm/post.h> |
Graeme Russ | 25391d1 | 2011-02-12 15:11:30 +1100 | [diff] [blame] | 40 | #include <asm/processor.h> |
Graeme Russ | 93efcb2 | 2011-02-12 15:11:32 +1100 | [diff] [blame] | 41 | #include <asm/processor-flags.h> |
Graeme Russ | 278638d | 2008-12-07 10:29:02 +1100 | [diff] [blame] | 42 | #include <asm/interrupt.h> |
Bin Meng | f17cea6 | 2015-04-24 18:10:04 +0800 | [diff] [blame] | 43 | #include <asm/tables.h> |
Gabe Black | 6ed1888 | 2011-11-16 23:32:50 +0000 | [diff] [blame] | 44 | #include <linux/compiler.h> |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 45 | |
Bin Meng | 035c1d2 | 2014-11-09 22:18:56 +0800 | [diff] [blame] | 46 | DECLARE_GLOBAL_DATA_PTR; |
| 47 | |
Bin Meng | 035c1d2 | 2014-11-09 22:18:56 +0800 | [diff] [blame] | 48 | static const char *const x86_vendor_name[] = { |
| 49 | [X86_VENDOR_INTEL] = "Intel", |
| 50 | [X86_VENDOR_CYRIX] = "Cyrix", |
| 51 | [X86_VENDOR_AMD] = "AMD", |
| 52 | [X86_VENDOR_UMC] = "UMC", |
| 53 | [X86_VENDOR_NEXGEN] = "NexGen", |
| 54 | [X86_VENDOR_CENTAUR] = "Centaur", |
| 55 | [X86_VENDOR_RISE] = "Rise", |
| 56 | [X86_VENDOR_TRANSMETA] = "Transmeta", |
| 57 | [X86_VENDOR_NSC] = "NSC", |
| 58 | [X86_VENDOR_SIS] = "SiS", |
| 59 | }; |
| 60 | |
Gabe Black | 846d08e | 2012-10-20 12:33:10 +0000 | [diff] [blame] | 61 | int __weak x86_cleanup_before_linux(void) |
| 62 | { |
Simon Glass | bcc28da | 2013-04-17 16:13:35 +0000 | [diff] [blame] | 63 | #ifdef CONFIG_BOOTSTAGE_STASH |
Simon Glass | 5322d62 | 2015-03-02 17:04:37 -0700 | [diff] [blame] | 64 | bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, |
Simon Glass | bcc28da | 2013-04-17 16:13:35 +0000 | [diff] [blame] | 65 | CONFIG_BOOTSTAGE_STASH_SIZE); |
| 66 | #endif |
| 67 | |
Gabe Black | 846d08e | 2012-10-20 12:33:10 +0000 | [diff] [blame] | 68 | return 0; |
| 69 | } |
| 70 | |
Graeme Russ | 6e25600 | 2011-12-27 22:46:43 +1100 | [diff] [blame] | 71 | int x86_init_cache(void) |
| 72 | { |
| 73 | enable_caches(); |
| 74 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 75 | return 0; |
| 76 | } |
Graeme Russ | 6e25600 | 2011-12-27 22:46:43 +1100 | [diff] [blame] | 77 | int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 78 | |
Wolfgang Denk | 6262d021 | 2010-06-28 22:00:46 +0200 | [diff] [blame] | 79 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 80 | { |
Graeme Russ | fdee8b1 | 2011-11-08 02:33:13 +0000 | [diff] [blame] | 81 | printf("resetting ...\n"); |
Graeme Russ | 45fc1d8 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 82 | |
| 83 | /* wait 50 ms */ |
| 84 | udelay(50000); |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 85 | disable_interrupts(); |
| 86 | reset_cpu(0); |
| 87 | |
| 88 | /*NOTREACHED*/ |
| 89 | return 0; |
| 90 | } |
| 91 | |
Graeme Russ | fdee8b1 | 2011-11-08 02:33:13 +0000 | [diff] [blame] | 92 | void flush_cache(unsigned long dummy1, unsigned long dummy2) |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 93 | { |
| 94 | asm("wbinvd\n"); |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 95 | } |
Graeme Russ | 278638d | 2008-12-07 10:29:02 +1100 | [diff] [blame] | 96 | |
Simon Glass | 8337433 | 2014-11-06 13:20:08 -0700 | [diff] [blame] | 97 | __weak void reset_cpu(ulong addr) |
Graeme Russ | 278638d | 2008-12-07 10:29:02 +1100 | [diff] [blame] | 98 | { |
Simon Glass | e0e7bd0 | 2015-04-28 20:11:29 -0600 | [diff] [blame] | 99 | /* Do a hard reset through the chipset's reset control register */ |
Simon Glass | 8b73e9f | 2016-03-11 22:06:59 -0700 | [diff] [blame] | 100 | outb(SYS_RST | RST_CPU, IO_PORT_RESET); |
Simon Glass | e0e7bd0 | 2015-04-28 20:11:29 -0600 | [diff] [blame] | 101 | for (;;) |
| 102 | cpu_hlt(); |
| 103 | } |
| 104 | |
| 105 | void x86_full_reset(void) |
| 106 | { |
Simon Glass | 8b73e9f | 2016-03-11 22:06:59 -0700 | [diff] [blame] | 107 | outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET); |
Graeme Russ | 278638d | 2008-12-07 10:29:02 +1100 | [diff] [blame] | 108 | } |
Stefan Reinauer | 2acf848 | 2012-12-02 04:49:50 +0000 | [diff] [blame] | 109 | |
Stefan Reinauer | 2acf848 | 2012-12-02 04:49:50 +0000 | [diff] [blame] | 110 | /* Define these functions to allow ehch-hcd to function */ |
| 111 | void flush_dcache_range(unsigned long start, unsigned long stop) |
| 112 | { |
| 113 | } |
| 114 | |
| 115 | void invalidate_dcache_range(unsigned long start, unsigned long stop) |
| 116 | { |
| 117 | } |
Simon Glass | 2baa3bb | 2013-02-28 19:26:11 +0000 | [diff] [blame] | 118 | |
| 119 | void dcache_enable(void) |
| 120 | { |
| 121 | enable_caches(); |
| 122 | } |
| 123 | |
| 124 | void dcache_disable(void) |
| 125 | { |
| 126 | disable_caches(); |
| 127 | } |
| 128 | |
| 129 | void icache_enable(void) |
| 130 | { |
| 131 | } |
| 132 | |
| 133 | void icache_disable(void) |
| 134 | { |
| 135 | } |
| 136 | |
| 137 | int icache_status(void) |
| 138 | { |
| 139 | return 1; |
| 140 | } |
Simon Glass | d8d9fec | 2014-10-10 08:21:52 -0600 | [diff] [blame] | 141 | |
Bin Meng | 035c1d2 | 2014-11-09 22:18:56 +0800 | [diff] [blame] | 142 | const char *cpu_vendor_name(int vendor) |
| 143 | { |
| 144 | const char *name; |
| 145 | name = "<invalid cpu vendor>"; |
| 146 | if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && |
| 147 | (x86_vendor_name[vendor] != 0)) |
| 148 | name = x86_vendor_name[vendor]; |
Simon Glass | 2f2efbc | 2014-10-10 08:21:54 -0600 | [diff] [blame] | 149 | |
Bin Meng | 035c1d2 | 2014-11-09 22:18:56 +0800 | [diff] [blame] | 150 | return name; |
Simon Glass | 2f2efbc | 2014-10-10 08:21:54 -0600 | [diff] [blame] | 151 | } |
| 152 | |
Simon Glass | 543bb14 | 2014-11-10 18:00:26 -0700 | [diff] [blame] | 153 | char *cpu_get_name(char *name) |
Simon Glass | 2f2efbc | 2014-10-10 08:21:54 -0600 | [diff] [blame] | 154 | { |
Simon Glass | 543bb14 | 2014-11-10 18:00:26 -0700 | [diff] [blame] | 155 | unsigned int *name_as_ints = (unsigned int *)name; |
Bin Meng | 035c1d2 | 2014-11-09 22:18:56 +0800 | [diff] [blame] | 156 | struct cpuid_result regs; |
Simon Glass | 543bb14 | 2014-11-10 18:00:26 -0700 | [diff] [blame] | 157 | char *ptr; |
Bin Meng | 035c1d2 | 2014-11-09 22:18:56 +0800 | [diff] [blame] | 158 | int i; |
Simon Glass | 2f2efbc | 2014-10-10 08:21:54 -0600 | [diff] [blame] | 159 | |
Simon Glass | 543bb14 | 2014-11-10 18:00:26 -0700 | [diff] [blame] | 160 | /* This bit adds up to 48 bytes */ |
Bin Meng | 035c1d2 | 2014-11-09 22:18:56 +0800 | [diff] [blame] | 161 | for (i = 0; i < 3; i++) { |
| 162 | regs = cpuid(0x80000002 + i); |
| 163 | name_as_ints[i * 4 + 0] = regs.eax; |
| 164 | name_as_ints[i * 4 + 1] = regs.ebx; |
| 165 | name_as_ints[i * 4 + 2] = regs.ecx; |
| 166 | name_as_ints[i * 4 + 3] = regs.edx; |
| 167 | } |
Simon Glass | 543bb14 | 2014-11-10 18:00:26 -0700 | [diff] [blame] | 168 | name[CPU_MAX_NAME_LEN - 1] = '\0'; |
Simon Glass | 2f2efbc | 2014-10-10 08:21:54 -0600 | [diff] [blame] | 169 | |
Bin Meng | 035c1d2 | 2014-11-09 22:18:56 +0800 | [diff] [blame] | 170 | /* Skip leading spaces. */ |
Simon Glass | 543bb14 | 2014-11-10 18:00:26 -0700 | [diff] [blame] | 171 | ptr = name; |
| 172 | while (*ptr == ' ') |
| 173 | ptr++; |
Bin Meng | 035c1d2 | 2014-11-09 22:18:56 +0800 | [diff] [blame] | 174 | |
Simon Glass | 543bb14 | 2014-11-10 18:00:26 -0700 | [diff] [blame] | 175 | return ptr; |
Simon Glass | 2f2efbc | 2014-10-10 08:21:54 -0600 | [diff] [blame] | 176 | } |
| 177 | |
Simon Glass | 543bb14 | 2014-11-10 18:00:26 -0700 | [diff] [blame] | 178 | int default_print_cpuinfo(void) |
Simon Glass | 2f2efbc | 2014-10-10 08:21:54 -0600 | [diff] [blame] | 179 | { |
Bin Meng | 035c1d2 | 2014-11-09 22:18:56 +0800 | [diff] [blame] | 180 | printf("CPU: %s, vendor %s, device %xh\n", |
| 181 | cpu_has_64bit() ? "x86_64" : "x86", |
| 182 | cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); |
Simon Glass | 2f2efbc | 2014-10-10 08:21:54 -0600 | [diff] [blame] | 183 | |
Bin Meng | ef61f77 | 2017-04-21 07:24:32 -0700 | [diff] [blame] | 184 | #ifdef CONFIG_HAVE_ACPI_RESUME |
| 185 | debug("ACPI previous sleep state: %s\n", |
| 186 | acpi_ss_string(gd->arch.prev_sleep_state)); |
| 187 | #endif |
| 188 | |
Simon Glass | 2f2efbc | 2014-10-10 08:21:54 -0600 | [diff] [blame] | 189 | return 0; |
| 190 | } |
Simon Glass | 463fac2 | 2014-10-10 08:21:55 -0600 | [diff] [blame] | 191 | |
Simon Glass | 9f0afe7 | 2014-11-12 22:42:26 -0700 | [diff] [blame] | 192 | void show_boot_progress(int val) |
| 193 | { |
Simon Glass | 9f0afe7 | 2014-11-12 22:42:26 -0700 | [diff] [blame] | 194 | outb(val, POST_PORT); |
| 195 | } |
Bin Meng | f17cea6 | 2015-04-24 18:10:04 +0800 | [diff] [blame] | 196 | |
| 197 | #ifndef CONFIG_SYS_COREBOOT |
Bin Meng | 2f8560c | 2016-05-11 07:44:56 -0700 | [diff] [blame] | 198 | /* |
| 199 | * Implement a weak default function for boards that optionally |
| 200 | * need to clean up the system before jumping to the kernel. |
| 201 | */ |
| 202 | __weak void board_final_cleanup(void) |
| 203 | { |
| 204 | } |
| 205 | |
Bin Meng | f17cea6 | 2015-04-24 18:10:04 +0800 | [diff] [blame] | 206 | int last_stage_init(void) |
| 207 | { |
Bin Meng | 159661d | 2017-04-21 07:24:41 -0700 | [diff] [blame] | 208 | board_final_cleanup(); |
| 209 | |
Bin Meng | 710d215 | 2017-04-21 07:24:37 -0700 | [diff] [blame] | 210 | #if CONFIG_HAVE_ACPI_RESUME |
Bin Meng | 280aebe | 2017-04-21 07:24:44 -0700 | [diff] [blame] | 211 | struct acpi_fadt *fadt = acpi_find_fadt(); |
Bin Meng | 710d215 | 2017-04-21 07:24:37 -0700 | [diff] [blame] | 212 | |
Bin Meng | 280aebe | 2017-04-21 07:24:44 -0700 | [diff] [blame] | 213 | if (fadt != NULL && gd->arch.prev_sleep_state == ACPI_S3) |
| 214 | acpi_resume(fadt); |
Bin Meng | 710d215 | 2017-04-21 07:24:37 -0700 | [diff] [blame] | 215 | #endif |
| 216 | |
Bin Meng | f17cea6 | 2015-04-24 18:10:04 +0800 | [diff] [blame] | 217 | write_tables(); |
| 218 | |
| 219 | return 0; |
| 220 | } |
| 221 | #endif |
Simon Glass | 02fe5e6 | 2015-04-29 22:26:01 -0600 | [diff] [blame] | 222 | |
Simon Glass | 0aa7bfa | 2016-01-17 16:11:28 -0700 | [diff] [blame] | 223 | static int x86_init_cpus(void) |
Simon Glass | 02fe5e6 | 2015-04-29 22:26:01 -0600 | [diff] [blame] | 224 | { |
Bin Meng | f967f9a | 2015-06-17 11:15:36 +0800 | [diff] [blame] | 225 | #ifdef CONFIG_SMP |
| 226 | debug("Init additional CPUs\n"); |
| 227 | x86_mp_init(); |
Bin Meng | 8972776 | 2015-07-22 01:21:12 -0700 | [diff] [blame] | 228 | #else |
| 229 | struct udevice *dev; |
| 230 | |
| 231 | /* |
| 232 | * This causes the cpu-x86 driver to be probed. |
| 233 | * We don't check return value here as we want to allow boards |
| 234 | * which have not been converted to use cpu uclass driver to boot. |
| 235 | */ |
| 236 | uclass_first_device(UCLASS_CPU, &dev); |
Bin Meng | f967f9a | 2015-06-17 11:15:36 +0800 | [diff] [blame] | 237 | #endif |
| 238 | |
Simon Glass | 02fe5e6 | 2015-04-29 22:26:01 -0600 | [diff] [blame] | 239 | return 0; |
| 240 | } |
| 241 | |
| 242 | int cpu_init_r(void) |
| 243 | { |
Simon Glass | 00431f6 | 2016-01-17 16:11:30 -0700 | [diff] [blame] | 244 | struct udevice *dev; |
| 245 | int ret; |
| 246 | |
| 247 | if (!ll_boot_init()) |
| 248 | return 0; |
| 249 | |
| 250 | ret = x86_init_cpus(); |
| 251 | if (ret) |
| 252 | return ret; |
| 253 | |
| 254 | /* |
| 255 | * Set up the northbridge, PCH and LPC if available. Note that these |
| 256 | * may have had some limited pre-relocation init if they were probed |
| 257 | * before relocation, but this is post relocation. |
| 258 | */ |
| 259 | uclass_first_device(UCLASS_NORTHBRIDGE, &dev); |
| 260 | uclass_first_device(UCLASS_PCH, &dev); |
| 261 | uclass_first_device(UCLASS_LPC, &dev); |
Simon Glass | 2b6d80b | 2015-08-04 12:34:00 -0600 | [diff] [blame] | 262 | |
Bin Meng | a455964 | 2016-06-08 05:07:38 -0700 | [diff] [blame] | 263 | /* Set up pin control if available */ |
| 264 | ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); |
| 265 | debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret); |
| 266 | |
Simon Glass | 2b6d80b | 2015-08-04 12:34:00 -0600 | [diff] [blame] | 267 | return 0; |
Simon Glass | 02fe5e6 | 2015-04-29 22:26:01 -0600 | [diff] [blame] | 268 | } |
Bin Meng | 1141fcf | 2016-05-11 07:45:00 -0700 | [diff] [blame] | 269 | |
| 270 | #ifndef CONFIG_EFI_STUB |
| 271 | int reserve_arch(void) |
| 272 | { |
| 273 | #ifdef CONFIG_ENABLE_MRC_CACHE |
Bin Meng | 1c9da37 | 2016-05-11 07:45:01 -0700 | [diff] [blame] | 274 | mrccache_reserve(); |
| 275 | #endif |
| 276 | |
| 277 | #ifdef CONFIG_SEABIOS |
| 278 | high_table_reserve(); |
Bin Meng | 1141fcf | 2016-05-11 07:45:00 -0700 | [diff] [blame] | 279 | #endif |
Bin Meng | 1c9da37 | 2016-05-11 07:45:01 -0700 | [diff] [blame] | 280 | |
Bin Meng | 353f5cb | 2017-04-21 07:24:47 -0700 | [diff] [blame] | 281 | #ifdef CONFIG_HAVE_ACPI_RESUME |
| 282 | acpi_s3_reserve(); |
| 283 | |
| 284 | #ifdef CONFIG_HAVE_FSP |
Bin Meng | cf20030 | 2017-04-21 07:24:39 -0700 | [diff] [blame] | 285 | /* |
| 286 | * Save stack address to CMOS so that at next S3 boot, |
| 287 | * we can use it as the stack address for fsp_contiue() |
| 288 | */ |
| 289 | fsp_save_s3_stack(); |
Bin Meng | 353f5cb | 2017-04-21 07:24:47 -0700 | [diff] [blame] | 290 | #endif /* CONFIG_HAVE_FSP */ |
| 291 | #endif /* CONFIG_HAVE_ACPI_RESUME */ |
Bin Meng | cf20030 | 2017-04-21 07:24:39 -0700 | [diff] [blame] | 292 | |
Bin Meng | 1c9da37 | 2016-05-11 07:45:01 -0700 | [diff] [blame] | 293 | return 0; |
Bin Meng | 1141fcf | 2016-05-11 07:45:00 -0700 | [diff] [blame] | 294 | } |
| 295 | #endif |