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wdenk9b7f3842003-10-09 20:09:04 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk9b7f3842003-10-09 20:09:04 +00006 */
7
8/*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
wdenk9b7f3842003-10-09 20:09:04 +000015#define CONFIG_DBAU1X00 1
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090016#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
wdenk9b7f3842003-10-09 20:09:04 +000017
Daniel Schwierzeck2bc7eeb2014-11-15 23:30:01 +010018#define CONFIG_DISPLAY_BOARDINFO
19
wdenk4ea537d2003-12-07 18:32:37 +000020#ifdef CONFIG_DBAU1000
wdenk9b7f3842003-10-09 20:09:04 +000021/* Also known as Merlot */
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090022#define CONFIG_SOC_AU1000 1
wdenk4ea537d2003-12-07 18:32:37 +000023#else
24#ifdef CONFIG_DBAU1100
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090025#define CONFIG_SOC_AU1100 1
wdenk4ea537d2003-12-07 18:32:37 +000026#else
27#ifdef CONFIG_DBAU1500
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090028#define CONFIG_SOC_AU1500 1
wdenk1ebf41e2004-01-02 14:00:00 +000029#else
wdenk96c7a8c2005-01-09 22:28:56 +000030#ifdef CONFIG_DBAU1550
31/* Cabernet */
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090032#define CONFIG_SOC_AU1550 1
wdenk96c7a8c2005-01-09 22:28:56 +000033#else
wdenk4ea537d2003-12-07 18:32:37 +000034#error "No valid board set"
35#endif
36#endif
37#endif
wdenk96c7a8c2005-01-09 22:28:56 +000038#endif
wdenk9b7f3842003-10-09 20:09:04 +000039
wdenk9b7f3842003-10-09 20:09:04 +000040
41#define CONFIG_BAUDRATE 115200
42
43/* valid baudrates */
wdenk9b7f3842003-10-09 20:09:04 +000044
45#define CONFIG_TIMESTAMP /* Print image info with timestamp */
46#undef CONFIG_BOOTARGS
47
48#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010049 "addmisc=setenv bootargs ${bootargs} " \
50 "console=ttyS0,${baudrate} " \
wdenk9b7f3842003-10-09 20:09:04 +000051 "panic=1\0" \
52 "bootfile=/tftpboot/vmlinux.srec\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010053 "load=tftp 80500000 ${u-boot}\0" \
wdenk9b7f3842003-10-09 20:09:04 +000054 ""
wdenk96c7a8c2005-01-09 22:28:56 +000055
56#ifdef CONFIG_DBAU1550
57/* Boot from flash by default, revert to bootp */
58#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
wdenk96c7a8c2005-01-09 22:28:56 +000059#else /* CONFIG_DBAU1550 */
Heiko Schocher65d4f8b2006-04-11 14:53:29 +020060#define CONFIG_BOOTCOMMAND "bootp;bootm"
wdenk96c7a8c2005-01-09 22:28:56 +000061#endif /* CONFIG_DBAU1550 */
62
Jon Loeligerb15a23b2007-07-04 22:32:03 -050063/*
Jon Loeligere54e77a2007-07-10 09:29:01 -050064 * BOOTP options
65 */
66#define CONFIG_BOOTP_BOOTFILESIZE
67#define CONFIG_BOOTP_BOOTPATH
68#define CONFIG_BOOTP_GATEWAY
69#define CONFIG_BOOTP_HOSTNAME
70
Jon Loeligere54e77a2007-07-10 09:29:01 -050071/*
Jon Loeligerb15a23b2007-07-04 22:32:03 -050072 * Command line configuration.
73 */
Jon Loeligerb15a23b2007-07-04 22:32:03 -050074#undef CONFIG_CMD_BEDBUG
Jon Loeligerb15a23b2007-07-04 22:32:03 -050075
76#ifdef CONFIG_DBAU1550
77
Jon Loeligerb15a23b2007-07-04 22:32:03 -050078#undef CONFIG_CMD_IDE
Jon Loeligerb15a23b2007-07-04 22:32:03 -050079#undef CONFIG_CMD_PCMCIA
80
81#else
82
83#define CONFIG_CMD_IDE
Jon Loeligerb15a23b2007-07-04 22:32:03 -050084
Jon Loeligerb15a23b2007-07-04 22:32:03 -050085#endif
86
wdenk9b7f3842003-10-09 20:09:04 +000087/*
88 * Miscellaneous configurable options
89 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk96c7a8c2005-01-09 22:28:56 +000091
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
93#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
94#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
wdenk9b7f3842003-10-09 20:09:04 +000095
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_MALLOC_LEN 128*1024
wdenk9b7f3842003-10-09 20:09:04 +000097
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
wdenk9b7f3842003-10-09 20:09:04 +000099
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_MHZ 396
wdenk96c7a8c2005-01-09 22:28:56 +0000101
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102#if (CONFIG_SYS_MHZ % 12) != 0
wdenk96c7a8c2005-01-09 22:28:56 +0000103#error "Invalid CPU frequency - must be multiple of 12!"
104#endif
105
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Shinya Kuribayashi5d374e02008-06-05 22:29:00 +0900107
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
wdenk9b7f3842003-10-09 20:09:04 +0000109
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
wdenk9b7f3842003-10-09 20:09:04 +0000111
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#define CONFIG_SYS_MEMTEST_START 0x80100000
113#define CONFIG_SYS_MEMTEST_END 0x80800000
wdenk9b7f3842003-10-09 20:09:04 +0000114
115/*-----------------------------------------------------------------------
116 * FLASH and environment organization
117 */
wdenk96c7a8c2005-01-09 22:28:56 +0000118#ifdef CONFIG_DBAU1550
119
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
121#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
wdenk96c7a8c2005-01-09 22:28:56 +0000122
123#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
124#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
125
wdenk96c7a8c2005-01-09 22:28:56 +0000126#else /* CONFIG_DBAU1550 */
127
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200128#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
129#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
wdenk9b7f3842003-10-09 20:09:04 +0000130
131#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
132#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
133
wdenk96c7a8c2005-01-09 22:28:56 +0000134#endif /* CONFIG_DBAU1550 */
135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
Heiko Schocher65d4f8b2006-04-11 14:53:29 +0200137
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200139#define CONFIG_FLASH_CFI_DRIVER 1
wdenk96c7a8c2005-01-09 22:28:56 +0000140
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200141#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_MONITOR_LEN (192 << 10)
wdenk9b7f3842003-10-09 20:09:04 +0000143
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
wdenk9b7f3842003-10-09 20:09:04 +0000145
146/* We boot from this flash, selected with dip switch */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
wdenk9b7f3842003-10-09 20:09:04 +0000148
149/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
151#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk9b7f3842003-10-09 20:09:04 +0000152
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200153#define CONFIG_ENV_IS_NOWHERE 1
wdenk9b7f3842003-10-09 20:09:04 +0000154
155/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200156#define CONFIG_ENV_ADDR 0xB0030000
157#define CONFIG_ENV_SIZE 0x10000
wdenk9b7f3842003-10-09 20:09:04 +0000158
159#define CONFIG_FLASH_16BIT
160
161#define CONFIG_NR_DRAM_BANKS 2
162
wdenk96c7a8c2005-01-09 22:28:56 +0000163#ifdef CONFIG_DBAU1550
164#define MEM_SIZE 192
165#else
166#define MEM_SIZE 64
167#endif
168
wdenk9b7f3842003-10-09 20:09:04 +0000169#define CONFIG_MEMSIZE_IN_BYTES
170
wdenk96c7a8c2005-01-09 22:28:56 +0000171#ifndef CONFIG_DBAU1550
wdenk9b7f3842003-10-09 20:09:04 +0000172/*---ATA PCMCIA ------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
174#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
wdenk9b7f3842003-10-09 20:09:04 +0000175#define CONFIG_PCMCIA_SLOT_A
176
177#define CONFIG_ATAPI 1
178#define CONFIG_MAC_PARTITION 1
179
180/* We run CF in "true ide" mode or a harddrive via pcmcia */
181#define CONFIG_IDE_PCMCIA 1
182
183/* We only support one slot for now */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
185#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk9b7f3842003-10-09 20:09:04 +0000186
187#undef CONFIG_IDE_LED /* LED for ide not supported */
188#undef CONFIG_IDE_RESET /* reset for ide not supported */
189
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk9b7f3842003-10-09 20:09:04 +0000191
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk9b7f3842003-10-09 20:09:04 +0000193
wdenk1ebf41e2004-01-02 14:00:00 +0000194/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_ATA_DATA_OFFSET 8
wdenk9b7f3842003-10-09 20:09:04 +0000196
197/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_ATA_REG_OFFSET 0
wdenk9b7f3842003-10-09 20:09:04 +0000199
200/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk96c7a8c2005-01-09 22:28:56 +0000202#endif /* CONFIG_DBAU1550 */
wdenk9b7f3842003-10-09 20:09:04 +0000203
wdenk9b7f3842003-10-09 20:09:04 +0000204#endif /* __CONFIG_H */