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git01.mediatek.com / filogic / uboot / b5bb139116ffb1ca3229e0793d48d6c34e450cb7 / . / board / cerf250 / memsetup.S
blob: f3d373a8a24c2190f4ca72b7020aaf6faae58918 [file] [log] [blame]
wdenkb5bb1392004-07-10 23:11:10 +0000[diff] [blame^]1/*
2 * Most of this taken from Redboot hal_platform_setup.h with cleanup
3 *
4 * NOTE: I haven't clean this up considerably, just enough to get it
5 * running. See hal_platform_setup.h for the source. See
6 * board/cradle/memsetup.S for another PXA250 setup that is
7 * much cleaner.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <config.h>
29#include <version.h>
30#include <asm/arch/pxa-regs.h>
31
32DRAM_SIZE: .long CFG_DRAM_SIZE
33
34/* wait for coprocessor write complete */
35 .macro CPWAIT reg
36 mrc p15,0,\reg,c2,c0,0
37 mov \reg,\reg
38 sub pc,pc,#4
39 .endm
40
41
42/*
43 * Memory setup
44 */
45
46.globl memsetup
47memsetup:
48
49 /* Set up GPIO pins first ----------------------------------------- */
50
51 ldr r0, =GPSR0
52 ldr r1, =CFG_GPSR0_VAL
53 str r1, [r0]
54
55 ldr r0, =GPSR1
56 ldr r1, =CFG_GPSR1_VAL
57 str r1, [r0]
58
59 ldr r0, =GPSR2
60 ldr r1, =CFG_GPSR2_VAL
61 str r1, [r0]
62
63 ldr r0, =GPCR0
64 ldr r1, =CFG_GPCR0_VAL
65 str r1, [r0]
66
67 ldr r0, =GPCR1
68 ldr r1, =CFG_GPCR1_VAL
69 str r1, [r0]
70
71 ldr r0, =GPCR2
72 ldr r1, =CFG_GPCR2_VAL
73 str r1, [r0]
74
75 ldr r0, =GPDR0
76 ldr r1, =CFG_GPDR0_VAL
77 str r1, [r0]
78
79 ldr r0, =GPDR1
80 ldr r1, =CFG_GPDR1_VAL
81 str r1, [r0]
82
83 ldr r0, =GPDR2
84 ldr r1, =CFG_GPDR2_VAL
85 str r1, [r0]
86
87 ldr r0, =GAFR0_L
88 ldr r1, =CFG_GAFR0_L_VAL
89 str r1, [r0]
90
91 ldr r0, =GAFR0_U
92 ldr r1, =CFG_GAFR0_U_VAL
93 str r1, [r0]
94
95 ldr r0, =GAFR1_L
96 ldr r1, =CFG_GAFR1_L_VAL
97 str r1, [r0]
98
99 ldr r0, =GAFR1_U
100 ldr r1, =CFG_GAFR1_U_VAL
101 str r1, [r0]
102
103 ldr r0, =GAFR2_L
104 ldr r1, =CFG_GAFR2_L_VAL
105 str r1, [r0]
106
107 ldr r0, =GAFR2_U
108 ldr r1, =CFG_GAFR2_U_VAL
109 str r1, [r0]
110
111 ldr r0, =PSSR /* enable GPIO pins */
112 ldr r1, =CFG_PSSR_VAL
113 str r1, [r0]
114
115 /* ---------------------------------------------------------------- */
116 /* Enable memory interface */
117 /* */
118 /* The sequence below is based on the recommended init steps */
119 /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
120 /* Chapter 10. */
121 /* ---------------------------------------------------------------- */
122
123 /* ---------------------------------------------------------------- */
124 /* Step 1: Wait for at least 200 microsedonds to allow internal */
125 /* clocks to settle. Only necessary after hard reset... */
126 /* FIXME: can be optimized later */
127 /* ---------------------------------------------------------------- */
128
129 ldr r3, =OSCR /* reset the OS Timer Count to zero */
130 mov r2, #0
131 str r2, [r3]
132 ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
133 /* so 0x300 should be plenty */
1341:
135 ldr r2, [r3]
136 cmp r4, r2
137 bgt 1b
138
139mem_init:
140
141 ldr r1, =MEMC_BASE /* get memory controller base addr. */
142
143 /* ---------------------------------------------------------------- */
144 /* Step 2a: Initialize Asynchronous static memory controller */
145 /* ---------------------------------------------------------------- */
146
147 /* MSC registers: timing, bus width, mem type */
148
149 /* MSC0: nCS(0,1) */
150 ldr r2, =CFG_MSC0_VAL
151 str r2, [r1, #MSC0_OFFSET]
152 ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
153 /* that data latches */
154 /* MSC1: nCS(2,3) */
155 ldr r2, =CFG_MSC1_VAL
156 str r2, [r1, #MSC1_OFFSET]
157 ldr r2, [r1, #MSC1_OFFSET]
158
159 /* MSC2: nCS(4,5) */
160 ldr r2, =CFG_MSC2_VAL
161 str r2, [r1, #MSC2_OFFSET]
162 ldr r2, [r1, #MSC2_OFFSET]
163
164 /* ---------------------------------------------------------------- */
165 /* Step 2b: Initialize Card Interface */
166 /* ---------------------------------------------------------------- */
167
168 /* MECR: Memory Expansion Card Register */
169 ldr r2, =CFG_MECR_VAL
170 str r2, [r1, #MECR_OFFSET]
171 ldr r2, [r1, #MECR_OFFSET]
172
173 /* MCMEM0: Card Interface slot 0 timing */
174 ldr r2, =CFG_MCMEM0_VAL
175 str r2, [r1, #MCMEM0_OFFSET]
176 ldr r2, [r1, #MCMEM0_OFFSET]
177
178 /* MCMEM1: Card Interface slot 1 timing */
179 ldr r2, =CFG_MCMEM1_VAL
180 str r2, [r1, #MCMEM1_OFFSET]
181 ldr r2, [r1, #MCMEM1_OFFSET]
182
183 /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
184 ldr r2, =CFG_MCATT0_VAL
185 str r2, [r1, #MCATT0_OFFSET]
186 ldr r2, [r1, #MCATT0_OFFSET]
187
188 /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
189 ldr r2, =CFG_MCATT1_VAL
190 str r2, [r1, #MCATT1_OFFSET]
191 ldr r2, [r1, #MCATT1_OFFSET]
192
193 /* MCIO0: Card Interface I/O Space Timing, slot 0 */
194 ldr r2, =CFG_MCIO0_VAL
195 str r2, [r1, #MCIO0_OFFSET]
196 ldr r2, [r1, #MCIO0_OFFSET]
197
198 /* MCIO1: Card Interface I/O Space Timing, slot 1 */
199 ldr r2, =CFG_MCIO1_VAL
200 str r2, [r1, #MCIO1_OFFSET]
201 ldr r2, [r1, #MCIO1_OFFSET]
202
203 /* ---------------------------------------------------------------- */
204 /* Step 2c: Write FLYCNFG FIXME: what's that??? */
205 /* ---------------------------------------------------------------- */
206
207
208 /* ---------------------------------------------------------------- */
209 /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
210 /* ---------------------------------------------------------------- */
211
212 /* Before accessing MDREFR we need a valid DRI field, so we set */
213 /* this to power on defaults + DRI field, set SDRAM clocks free running */
214
215 ldr r3, =CFG_MDREFR_VAL
216 ldr r2, =0xFFF
217 and r3, r3, r2
218
219 ldr r0, [r1, #MDREFR_OFFSET]
220 bic r0, r0, r2
221 bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
222 orr r0, r0, r3
223
224 str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
225
226
227 /* ---------------------------------------------------------------- */
228 /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
229 /* ---------------------------------------------------------------- */
230
231 /* Initialize SXCNFG register. Assert the enable bits */
232
233 /* Write SXMRS to cause an MRS command to all enabled banks of */
234 /* synchronous static memory. Note that SXLCR need not be written */
235 /* at this time. */
236
237 /* FIXME: we use async mode for now */
238
239
240 /* ---------------------------------------------------------------- */
241 /* Step 4: Initialize SDRAM */
242 /* ---------------------------------------------------------------- */
243
244 /* set MDREFR according to user define with exception of a few bits */
245
246 ldr r4, =CFG_MDREFR_VAL
247 ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
248 MDREFR_K2RUN |MDREFR_K2DB2)
249 and r4, r4, r2
250 bic r0, r0, r2
251 orr r0, r0, r4
252
253 str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
254 ldr r0, [r1, #MDREFR_OFFSET]
255
256 /* Step 4b: de-assert MDREFR:SLFRSH. */
257
258 bic r0, r0, #(MDREFR_SLFRSH)
259 str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
260 ldr r0, [r1, #MDREFR_OFFSET]
261
262
263 /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */
264
265 ldr r4, =CFG_MDREFR_VAL
266 ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
267 MDREFR_K1FREE | MDREFR_K2FREE)
268 and r4, r4, r2
269 orr r0, r0, r4
270 str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
271 ldr r0, [r1, #MDREFR_OFFSET]
272
273
274 /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
275 /* configure but not enable each SDRAM partition pair. */
276
277 ldr r4, =CFG_MDCNFG_VAL
278 bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
279 bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
280 str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
281 ldr r4, [r1, #MDCNFG_OFFSET]
282
283
284 /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
285 /* 100..200 µsec. */
286
287 ldr r3, =OSCR /* reset the OS Timer Count to zero */
288 mov r2, #0
289 str r2, [r3]
290 ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
291 /* so 0x300 should be plenty */
2921:
293 ldr r2, [r3]
294 cmp r4, r2
295 bgt 1b
296
297
298 /* Step 4f: Trigger a number (usually 8) refresh cycles by */
299 /* attempting non-burst read or write accesses to disabled */
300 /* SDRAM, as commonly specified in the power up sequence */
301 /* documented in SDRAM data sheets. The address(es) used */
302 /* for this purpose must not be cacheable. */
303
304 ldr r3, =CFG_DRAM_BASE
305.rept 8
306 str r2, [r3]
307.endr
308
309 /* Step 4g: Write MDCNFG with enable bits asserted */
310 /* (MDCNFG:DEx set to 1). */
311
312 ldr r3, [r1, #MDCNFG_OFFSET]
313 orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
314 str r3, [r1, #MDCNFG_OFFSET]
315
316 /* Step 4h: Write MDMRS. */
317
318 ldr r2, =CFG_MDMRS_VAL
319 str r2, [r1, #MDMRS_OFFSET]
320
321
322 /* We are finished with Intel's memory controller initialisation */
323
324
325 /* ---------------------------------------------------------------- */
326 /* Disable (mask) all interrupts at interrupt controller */
327 /* ---------------------------------------------------------------- */
328
329initirqs:
330
331 mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
332 ldr r2, =ICLR
333 str r1, [r2]
334
335 ldr r2, =ICMR /* mask all interrupts at the controller */
336 str r1, [r2]
337
338
339 /* ---------------------------------------------------------------- */
340 /* Clock initialisation */
341 /* ---------------------------------------------------------------- */
342
343initclks:
344
345 /* Disable the peripheral clocks, and set the core clock frequency */
346
347 /* Turn Off ALL on-chip peripheral clocks for re-configuration */
348 /* Note: See label 'ENABLECLKS' for the re-enabling */
349 ldr r1, =CKEN
350 mov r2, #0
351 str r2, [r1]
352
353
354 /* default value in case no valid rotary switch setting is found */
355 ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
356
357 /* ... and write the core clock config register */
358 ldr r1, =CCCR
359 str r2, [r1]
360
361#ifdef RTC
362 /* enable the 32Khz oscillator for RTC and PowerManager */
363
364 ldr r1, =OSCC
365 mov r2, #OSCC_OON
366 str r2, [r1]
367
368 /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
369 /* has settled. */
37060:
371 ldr r2, [r1]
372 ands r2, r2, #1
373 beq 60b
374#endif
375
376 /* ---------------------------------------------------------------- */
377 /* */
378 /* ---------------------------------------------------------------- */
379
380 /* Save SDRAM size */
381 ldr r1, =DRAM_SIZE
382 str r8, [r1]
383
384 /* Interrupt init: Mask all interrupts */
385 ldr r0, =ICMR /* enable no sources */
386 mov r1, #0
387 str r1, [r0]
388
389 /* FIXME */
390
391#define NODEBUG
392#ifdef NODEBUG
393 /*Disable software and data breakpoints */
394 mov r0,#0
395 mcr p15,0,r0,c14,c8,0 /* ibcr0 */
396 mcr p15,0,r0,c14,c9,0 /* ibcr1 */
397 mcr p15,0,r0,c14,c4,0 /* dbcon */
398
399 /*Enable all debug functionality */
400 mov r0,#0x80000000
401 mcr p14,0,r0,c10,c0,0 /* dcsr */
402
403#endif
404
405 /* ---------------------------------------------------------------- */
406 /* End memsetup */
407 /* ---------------------------------------------------------------- */
408
409endmemsetup:
410
411 mov pc, lr